The Method of Reversible Circuits Design with One-gate Prediction

• Autorzy: Skorupski A.

Identyfikatory

DOI

10.24425/123556

• Języki publikacji: EN

Abstrakty

EN

This paper presents an original method of designing reversible circuits. This method is destined to most popular gate set with three types of gates CNT (Control, NOT and Toffoli). The presented algorithm based on graphical representation of the reversible function is called s-maps. This algorithm allows to find optimal or quasi-optimal reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. Especially the cascade of the gates as realization of reversible function is presented. In Section 2 there is introduced a classification of minterms distribution. The s-maps are the representation of the reversible functions where the minterms distribution is presented. The choice of the first gate in the cascade depends on possibility of improving the distribution. Section 3 describes the algorithm, namely how to find the optimal or quasi-optimal solutions of the given function.

Słowa kluczowe

EN

reversible logic; reversible circuits; reversible gates; CNT set of the gates

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2018
• Tom: Vol. 64, No. 4
• Strony: 535--540
• Opis fizyczny: Bibliogr. 8 poz., rys., tab.

Twórcy

autor

Skorupski A.

• Institute of Computer Science, Warsaw University of Technology

Bibliografia

• [1] O. Golubitsky and D. Maslov, “A study of optimal 4-bit reversible Toffoli circuits and their synthesis,” IEEE Transactions on Computers, vol. 61, no. 9, 2012,. pp. 1341-1353.
• [2] C. Bandyopadhyay, H. Rahaman, R. Drechsler, “A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit,” Proceedings of the IEEE International Symposium on Multiple-Valued Logic, pp. 109-114, May 19-21, 2014
• [3] C. S. Cheng, A. K. Singh, “Heuristic Synthesis of Reversible Logic - A Comparative Study”, Advances in Electrical and Electronic Engineering, vol. 12, no. 3, pp. 210-225, September 2014
• [4] M. Krishna, An. Chattopadhyay, “Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching”, Proceedings of the IEEE International Symposium on Multiple-Valued Logic, pp. 103-108, May 19-21, 2014
• [5] C.-C. Lin, N. K. Jha, “RMDDS: Reed-Muller Decision Diagram Synthesis of Reversible Logic Circuits”, ACM Journal on Emerging Technologies in Computing Systems, vol. 10, no. 2, pp. 14:1–14:25, February 2014
• [6] S. J. Roy, K. Datta, C. Bandyopadhyay, H. Rahaman, “A Transformation Based Heuristic Synthesis Approach for Reversible Circuits”, Proceedings of the International Conference on Advances in Electrical Engineering, pp. 1-5, January 2014.
• [7] E. Schönborn, K. Datta, R. Wille, I. Sengupta, H. Rahaman, R. Drechsler: “BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits”, International Conference on VLSI Design, 2015
• [8] A. Skorupski, “Graphical Method of Reversible Circuits Synthesis,”, IJET, Vol 63, No 3, 2017.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).