Architectural and structural and functional features of the organization of parallel-hierarchical memory

• Autorzy: Timchenko Leonid , Kokriatskaia Natalia , Tverdomed Volodymyr , Yepifanova Iryna Yu. , Didenko Yurii , Zhuk Dmytro , Kozyr Maksym , Shakhina Iryna

Identyfikatory

DOI

10.35784/iapgos.5615

Warianty tytułu

PL

Architektoniczne, strukturalne i funkcjonalne cechy równoległo-hierarchicznej organizacji pamięci

• Języki publikacji: EN

Abstrakty

EN

Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallelhierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory.

PL

Równoległa pamięć hierarchiczna (pamięć PI) jest nowym typem pamięci zaprojektowanym w celu poprawy wydajności równoległych systemów obliczeniowych. Pamięć PI składa się z dwóch bloków: maski RAM i ogon RAM. Maska RAM przechowuje maski używane do kodowania informacji, podczas gdy ogon RAM przechowuje rzeczywiste informacje. Blok adresowy pamięci PI jest odpowiedzialny za generowanie fizycznych adresów komórek, w których przechowywane są elementy końcowe i ich maski. Blok adresowy przechowuje również pole adresu, w którym tablica została zapisana i kojarzy to pole adresu z odpowiednim adresem zewnętrznym użytym do zapisu tablicy. Proponowana struktura bloku adresowego jest w stanie efektywnie generować fizyczne adresy komórek, w których przechowywane są elementy ogonowe i ich maski. Blok adresowy może również przechowywać pole adresu, w którym tablica została zapisana i powiązać to pole adresu z odpowiednim adresem zewnętrznym użytym do zapisu tablicy. Zaproponowana struktura bloku adresowego została zaimplementowana w prototypie pamięci PI. Wykazano, że prototyp pamięci PI jest w stanie znacznie poprawić wydajność w porównaniu z tradycyjnymi architekturami pamięci. W artykule zostanie przedstawiony szczegółowy opis algorytmu konwersji PI, opis różnych trybów adresowania, które mogą być używane w pamięci PI, analiza wydajności równoległo-hierarchicznych struktur pamięci oraz omówienie wyzwań i przyszłych kierunków badań w dziedzinie pamięci PI.

Słowa kluczowe

EN

parallel hierarchical memory; PI memory; address block; mask RAM; tail element RAM; performance improvement

PL

równoległa pamięć hierarchiczna; pamięć PI; blok adresowy; maska RAM; ogon RAM; poprawa wydajności

• Wydawca: Wydawnictwo Politechniki Lubelskiej
• Czasopismo: Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska
• Rocznik: 2024
• Tom: T. 14, nr 1
• Strony: 46--52
• Opis fizyczny: Bibliogr. 31 poz., rys.

Twórcy

autor

Timchenko Leonid

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0000-0001-5056-5913

autor

Kokriatskaia Natalia

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0000-0003-0090-3886

autor

Tverdomed Volodymyr

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0000-0002-0695-1304

autor

Yepifanova Iryna Yu.

• Vinnytsia National Technical Unіversity, Vinnytsia, Ukraine

• https://orcid.org/0000-0002-0391-9026

autor

Didenko Yurii

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0009-0008-1033-4238

autor

Zhuk Dmytro

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0000-0001-8951-5542

autor

Kozyr Maksym

• State University of Infrastructure and Technology, Kyiv, Ukraine

• https://orcid.org/0009-0007-2564-6552

autor

Shakhina Iryna

• Vinnytsia Mykhailo Kotsiubynskyi State Pedagogical University, Vinnytsia, Ukraine

• https://orcid.org/0000-0002-4318-6189

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