Pipelined architecture of a chaotic pseudo-random number generator in a Cyclone V SoC device

• Autorzy: Dąbal P. , Pełka R.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we present a novel, optimized microarchitecture of a pseudo-random number generator (PRNG) based on the chaotic model with frequency dependent negative resistances (FDNR). The project was focused on optimization of the PRNG architecture to achieve the highest possible output throughput of the generated pseudo-random sequences. As a result we got a model of the pipelined PRNG that was implemented in Cyclone V SoC from Altera and verified experimentally. All versions of the PRNG were tested by standard statistical tests NIST SP800-22. In addition, we also provide a brief comparison with the PRNG implementation in SoC from Xilinx.

Słowa kluczowe

EN

chaotic system; random number generators; FPGA; SoC

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2015
• Tom: Vol. 61, No. 7
• Strony: 287--289
• Opis fizyczny: Bibliogr. 6 poz., schem., tab., wzory

Twórcy

autor

Dąbal P.

• Military University of Technology, Faculty of Electronics, 2 Gen. Sylwestra Kaliskiego St., 00-908 Warszawa, Poland

autor

Pełka R.

• Military University of Technology, Faculty of Electronics, 2 Gen. Sylwestra Kaliskiego St., 00-908 Warszawa, Poland

Bibliografia

• [1] Elwakil A. S., Kennedy M. P.: Chaotic oscillator configuration using a frequency dependent negative resistor. In Proc. Int. Symp. on Circuits and Systems, vol. 5, pp. 399-402, 1999.
• [2] Rukhin A., et al.: A statistical test suite for random and pseudorandom number generators for cryptographic applications. NIST Special publication 800-22, Revision 1a, Aug. 2010.
• [3] Dabal P., Pelka R.: FPGA Implementation of Chaotic Pseudo-Random Bit Generators. 19th International Conference Mixed Design of Integrated Circuits and Systems. Warsaw, 2012.
• [4] Dabal P., Pelka R.: Fast pipelined pseudo-random number generator in programmable SoC device. International Conference on Signals and Electronic Systems, Poznań, 2014.
• [5] Dabal P., Pelka R.: An integrated system for statistical testing of pseudo-random generators in FPGA devices. International Conference on Signals and Electronic Systems, Wroclaw, 2012.
• [6] Barakat M. L., Mansingka A. S., Radwan A. G., Salama K. N.: Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators. ETRI Journal, vol. 35, no. 3, pp. 448-458, 2013.