Thermal modelling of modern processors using FEM and compact model

• Autorzy: Galicia M. , Zając P. , Maj C. , Szermer M. , Napieralski A.
• Języki publikacji: EN

Abstrakty

EN

A variety of thermal models has been proposed to predict the temperatures inside modern processors. In this paper, we describe and compare two such approaches, a detailed FEMbased simulation and a simpler architectural compact model. It is shown that both models provide comparable results when it comes to predicting the maximal temperature, however there are also non-negligible differences when estimating thermal gradients within a chip. Furthermore, transient simulation results show some differences in temperature profile during processor heating.

Słowa kluczowe

EN

thermal simulation; finite-element method; multi-core; thermal modelling

PL

symulacje termiczne; metoda elementów skończonych; wielordzeniowość; modelowanie cieplne

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2015
• Tom: Vol. 6, nr 3
• Strony: 110--116
• Opis fizyczny: Bibliogr. 11 poz., il. kolor., rys., wykr.

Twórcy

autor

Galicia M.

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lodz, Poland

autor

Zając P.

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lodz, Poland

autor

Maj C.

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lodz, Poland

autor

Szermer M.

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lodz, Poland

autor

Napieralski A.

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lodz, Poland

Bibliografia

• [1] International Technology Rodmap for Semiconductors (ITRS), 2009
• [2] ANSYS® Workbench™ 14, available at: http://www.ansys.com
• [3] COMSOL Multiphysics®, available at: http://www.comsol.com
• [4] M. Janicki, G. De Mey, and A. Napieralski, “Thermal analysis of layered electronic circuits with Green’s functions”, Microelectronics Journal, Vol. 38, pp. 177-184, 2007.
• [5] K. Skadron, M. R. Stan, W. Huang, S. Velusamy, D. Tarjan, and K. Sankaranarayanan, "Temperature-Aware Microarchitecture." In Proceedings of the 30th International Symposium on Computer Architecture, June 2003
• [6] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. “Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits”. Proceedings of the IEEE, 91(2):305-- 327, February 2003.
• [7] M. Janicki, P. Zając, M. Szermer, A. Napieralski "Influence of Scaling on IC Temperature in FinFET Microprocessor Technologies" 20th International Conference Mixed Design of Integrated Circuits and Systems, Gdynia, Poland, 20-22 June 2013
• [8] P. Zajac, M. Szermer, M. Janicki, C. Maj, P. Pietrzak, A. Napieralski, "Analysis of the effectiveness of core swapping in modern multicore processors," 19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC, pp.385-388, 25-27 Sept. 2013
• [9] A. Krum. Thermal management. In F . Kreith, editor, “The CRC handbook of thermal engineering”, pages 2.1–2.92. CRC Press, Boca Raton, FL, 2000
• [10] Guoping Xu, “Thermal Modeling Of Multi-Core Processors”, Thermal and Thermomechanical Phenomena in Electronics Systems, ITHERM The Tenth Intersociety Conference on, San Diego, CA, USA, pp. 100- 96, May 30-June 2, 2006
• [11] K. Skadron, Mn R. Stan et al., „Temperature-Aware Microarchitecture: Extended Discussion and Results”, University of Virginia, Departement of Computer Science, Technical report CS- 2003-08, April 2003