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Optimization of a logic circuit of the microprogrammed Moore machine with use of nano-PLA
Języki publikacji
Abstrakty
W artykule została przedstawiona metoda syntezy mikroprogramowanego automatu Moore'a implementowanego w układach nano-PLA. Metoda jest ukierunkowana na redukcję zasobów sprzętowych, potrzebnych do implementacji automatu Moore’a. Jest ona oparta na optymalnym kodowaniu stanów i rozbijaniu matrycy termów na dwie części. Takie podejście pozwala zmniejszyć liczbę linii w tablice przejść automatu Moore’a do odpowiedniej liczby linii w równoważnym automacie z wyjściami typu Mealy’ego.
The model of the microprogrammable Moore automaton [6] is often used during the digital control systems realization [1, 4]. The development of microelectronics has led to appearance of different programmable logic devices [13, 15, 18], which are used for implementing microprogrammable automaton (MPA) logic circuits. One of the important problems of MPA synthesis is the decrease in the chip space occupied by MPA logic circuit. Solution of this problem allows decreasing the power consumption and increasing the clock rate. The methods of solution of this problem depend strongly on logic elements used for implementing the MPA logic circuit [2, 3, 13, 15]. In this paper we discuss the case when nanoelectronic programmable logic arrays (PLA) are used for implementing Moore MPA logic circuit. The approach is connected with optimal state encoding and decomposition of a matrix of terms in two sub-matrices (Fig. 2). To do it, the classes of the pseudoequivalent states are used [1, 4]. Such an approach allows reducing the number of rows of the structure table of Moore MPA up to this value of the equivalent Mealy MPA. As a result the area of the matrices generating input memory functions is optimized. The example of application of the proposed methods is given.
Wydawca
Czasopismo
Rocznik
Tom
Strony
1186--1190
Opis fizyczny
Bibliogr. 18 poz., rys., wykr., wzory
Twórcy
autor
- Uniwersytet Zielonogórski, ul. Licealna 9, 65-417 Zielona Góra
autor
- Uniwersytet Zielonogórski, ul. Licealna 9, 65-417 Zielona Góra
autor
- Uniwersytet Zielonogórski, ul. Licealna 9, 65-417 Zielona Góra
Bibliografia
- [1] Baranov S.: Logic and system design of digital systems. Tallinn: TUT Press, 2008.
- [2] Baranov S.: Logic synthesis for control automata. Norwell, MA, USA: Kluwer Academic Publishers, 1994.
- [3] Baranov S., Levin I., Koren O., Karpovski M.: Designing fault tolerant FSM by nano-PLA. in Proc. of the 15th IEEE International On-Line Testing Symposium; 2009, Sembra-Lisbon, Portugal, 229-234.
- [4] Barkalov A.: Synthesis of Control Units on Programmable Logic Devices. DNTU, Donetsk, 2002, in Russian.
- [5] Barkalov A., Titarenko L.: Logic synthesis for FSM-based control units. Lecture notes in electrical engineering. Berlin: Springer Verlag Heidelberg, 2009, no. 53.
- [6] Barkalov A., Titarenko L., Hebda O.: Optimization of Moore finite-state-machine matrix circuit. Pomiary, Automatyka, Kontrola 2011; 57(8), 939-941.
- [7] DeMicheli G.: Synthesis and optimization of digital circuits. NY:McGraw-Hill, 1994.
- [8] DeMicheli G., Brayton R., Sangiovanni-Vincentelli A.: Optimal state assignment for finite state machines. IEEE Trans. on CAD 1985; 4, 269-284.
- [9] Novikov G.: About one approach for finite state machines research, Contr. Syst. Mach. 1974; 2, 70–75, (in Russian).
- [10] Hon A.D., Wilson M.: Nanowire-based sublithographic programmable logic arrays. International Journal of Applied Mathematics and Computer Sciences 2007; 17(4), 565–575.
- [11] Kania D., Czerwiski R.: Area and speed oriented synthesis of FSM for PAL-based CPLDs. Microprocessors and Microsystems 2012; 36(1), 45-61.
- [12] Levin I.: Decomposition design of automata based on PLA with memory. Automatic Control and Computer Sciences 1986; 20(2), 61-68.
- [13] Navabi Z.: Embedded core design with FPGA. NY: McGraw-Hill, 1997.
- [14] Shrestha A., Takaota A., Tayu S., Ueno S.: On two problems of nano-PLA design. IEEE Trans. on Informatics and Systems 2011; E94(1), 25-41.
- [15] Singh S., Singh R., Bhatia M.: Performance evaluation of hybrid reconfigurable computing architecture over symmetrical FPGAs. International Journal of Embedded Systems and Applications 2012; 2(3), 107-116.
- [16] Skliarova I., Sklyarov V., Sudnitson A.: Design of FPGA-based circuits using hierarchical finite state machines. Tallinn:TUTPress, 2008.
- [17] Sklyarov V.: Synthesis of automata with matrix VLSIs. Minsk: Nauka i Technika, 1984, (in Russian).
- [18] Website of the Xilinx Corporation; 2012. http://www.xilinx.com
Typ dokumentu
Bibliografia
Identyfikator YADDA
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