Hardware rough set processor parallel architecture in FPGA for finding core in big datasets

• Autorzy: Kopczyński Maciej , Grześ Tomasz

Identyfikatory

DOI

10.2478/jaiscr-2021-0007

• Języki publikacji: EN

Abstrakty

EN

This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

Słowa kluczowe

EN

rough sets; FPGA; core attributes; parallel architecture

• Wydawca: University of Social Sciences
• Czasopismo: Journal of Artificial Intelligence and Soft Computing Research
• Rocznik: 2021
• Tom: Vol. 11, No. 2
• Strony: 99--110
• Opis fizyczny: Bibliogr. 28 poz., rys.

Twórcy

autor

Kopczyński Maciej

• Faculty of Computer Science, Bialystok University of Technology

autor

Grześ Tomasz

• Faculty of Computer Science, Bialystok University of Technology

Bibliografia

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Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).