The architecture of a low phase noise low power Delta-Sigma Fractional-N synthesizer

• Autorzy: Siwiec Krzysztof , Pleskacz Witold A.
• Języki publikacji: EN

Abstrakty

EN

In this paper a new Delta Sigma Fractional N synthesizer architecture is presented. The synthesizer achieves low fractional spurs and quantization noise, which relaxes the trade-off between PLL bandwidth and phase noise. The proposed architecture is based on two delay lines, which are used to compensate the phase error resulting from fractional synthesis. Additionally, dedicated control and calibration circuitry is described. The synthesizer has been implemented in standard 130 nm CMOS technology, occupies 0.1S4 mm² silicon area and dissipates 3.6 mW of power from 1.2 V supply. Measurements show that the presented architecture achieves 30 dB phase noise reduction in comparison with a standard Delta Sigma Fractional N synthesizer. The integrated rms jitter is 2.76 ps and worst case fractional spur is -52 dBc.

Słowa kluczowe

EN

phase locked loop; PLL; Fractional-N; frequency synthesis; delay line; calibration

PL

pętla synchronizacji fazowej; PLL; synteza częstotliwości; linia opóźniająca; kalibracja

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2018
• Tom: Vol. 9, nr 4
• Strony: 161--166
• Opis fizyczny: Bibliogr. 16 poz., il. kolor., rys., wykr.

Twórcy

autor

Siwiec Krzysztof

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland

autor

Pleskacz Witold A.

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland

Bibliografia

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• [7] K. Siwiec, W.A. Pleskacz, "A low phase noise low power Fractional-N synthesizer architecture, " 2015 1st URSI Atlantic Radio Science Conference (URSI AT-RASC), Gran Canaria, Spain, 2015, pp. 1-1.
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• [12] H. Hedayati, W. Khalil and B. Bakkaloglu, "A 1 MHz Bandwidth, 6 GHz 0.18 μm CMOS Type-I ΔΣ Fractional-N Synthesizer for WiMAX Applications", IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3244-3252, Dec. 2009.
• [13] H. Y. Jian, Z. Xu, Y. C. Wu and M. C. F. Chang, "A Fractional-N PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 768-780, April 2010.
• [14] I. T. Lee, H. Y. Lu and S. I. Liu, "A 6-GHz All-Digital Fractional- N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique, " IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 5, pp. 267-271, May 2012.
• [15] C. Venerus and I. Galton, "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO, " IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 450-463, Feb. 2015.
• [16] T. Borejko, K. Siwiec, P. Narczyk, W. A. Pleskacz, "High frequency and frequency conversion chain for L1/E1 band for GPS/Galileo signal receiver, " Polish Patent Office, Registered Mask Work S-0019, December 19, 2016.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).