Design and realization of Two-Operand Modular Adders in the FPGA

• Autorzy: Smyk R. , Czyżak M.
• Konferencja: Computer Applications in Electrical Engineering 2012 (23-24.04.2012; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The paper presents the structure of modular adders implemented in the Xilinx environment with the use of the Virtex 6 family. Two types of adders are considered, one is for 5-bit moduli and the other is for 6-bit moduli. Their structures have been designed and experimental results have been shown.

Słowa kluczowe

EN

Two-Operand Modular Adders; TOMA; FPGA

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2012
• Tom: No. 71
• Strony: 209--216
• Opis fizyczny: Bibliogr. 9 poz., rys.

Twórcy

autor

Smyk R.

• Gdansk University of Technology

autor

Czyżak M.

• Gdansk University of Technology

Bibliografia

• [1] Szabo N., Tanaka R., Residue Arithmetic and Its Applications to Computer Technology, McGraw-Hill, New York, 1967.
• [2] Soderstrand M., Jenkins M., Jullien G., Taylor F., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986.
• [3] Banerji D., A Novel Implementation Method for Addition and Subtraction in Residue Number Systems, IEEE Transactions on Computers, Volume 23, Number 1, Pages 106-109, 1974.
• [4] Soderstrand M., A New Hardware Implementation of Modulo Adders for Residue Number Systems, Proc. IEEE 26th Midwest Symp. Circuits and Systems, Pages 412-415, August 1983.
• [5] Bayoumi M., Jullien G., A VLSI Implementation of Residue Adders, IEEE Trans. Circuits and Systems, Volume 34, Pages 284-288, March 1987.
• [6] Dugdale M., VLSI Implementation of Residue Adders Based Based On Binary Adders, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, Volume 39, Pages 325-329, May 1992.
• [7] Piestrak S., Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders, IEEE Trans. Computers, Volume 43, No. 1, Pages 68-77, January 1994.
• [8] Hiasat A. A., High-Speed and Reduced-Area Modular Adder Structures for RNS, IEEE Trans. Computers, Volume 51, No. 1, Pages 84-89, January 2002.
• [9] www.xilinx.com, Virtex-6 FPGA Configurable Logic Block, ug364, February 2012.