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Comparison of three different 2-D space vector PWM algorithms and their FPGA implementations

Wybrane pełne teksty z tego czasopisma
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
To improve the flexibility of the multilevel space vector pulse width modulation (SVPWM), various algorithms have been developed. A theoretical comparison is made for three 2-D SVPWM algorithms: they are g-h frame, α' - β' frame and multilevel SVPWM based on two-level (α* - β* frame). The aim is to provide a guideline for the selection of the most appropriate SVPWM technique for digital implementation. Among them, the α' - β' frame offers the best flexibility with the least calculation and is well suited for digital implementation. The α* - β* frame is the most intuitionistic but has the largest calculation. New general methods of the g-h frame and α' - β' frame for any level SVPWM are also provided, which needs only the angle θ and the modulation depth m to generate and arrange the final vector sequence. All three methods are implemented in a field programmable gate array (FPGA) with very high speed integrated circuit hardware description language (VHDL) and compared in terms of implementation complexity and logic resources required. Simulation results show the absolute advantages of α' - β' frame in briefness and resources use. Finally, an experimental test result is presented with a three-level neutral-point-clamped (NPC) inverter.
Rocznik
Strony
176--189
Opis fizyczny
Bibliogr. 33 poz., rys., tab., wykr.
Twórcy
autor
  • School of Information Science and Engineering, Central South University, Changsha 410083, China
  • School of Electrical and Information Engineering, Changsha University of Science and Technology, Changsha 410004, China
autor
  • School of Information Science and Engineering, Central South University, Changsha 410083, China
autor
  • School of Electrical and Information Engineering, Changsha University of Science and Technology, Changsha 410004, China
Bibliografia
  • [1] L. M. Tolbert, F. Z. Peng, T. G. Habetler, Multilevel converters for large electric drives, IEEE Trans. Ind. Appl. 35 (1) (1999) 36–44.
  • [2] J. Rodriguez, J.-S. Lai, F. Z. Peng, Multilevel inverters: A survey of topologies, controls, and applications, IEEE Trans. Ind. Electron. 49 (4) (2002) 724–738.
  • [3] J. Rodriguez, S. Bernet, B. Wu, J. Pontt, S. Kouro, Multilevel voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron. 54 (6) (2007) 2930–2945.
  • [4] E. P. Wiechmann, P. Aqueveque, R. Burgos, J. Rodriguez, On the efficiency of voltage source and current source inverters for high-power drives, IEEE Trans. Ind. Electron. 55 (4) (2008) 1771–1782.
  • [5] A. K. Gupta, A. M. Khambadkone, A space vector PWM scheme for multilevel inverters based on two-level space vector PWM, IEEE Trans. Ind. Electron. 53 (5) (2006) 1631–1639.
  • [6] A. R. Beig, G. Narayanan, V. T. Ranganathan, Modified SVPWM algorithm for three level VSI with synchronized and symmetrical waveforms, IEEE Trans. Ind. Electron. 54 (1) (2007) 486–494.
  • [7] A. K. Gupta, A. M. Khambadkone, A general space vector PWM algorithm for multilevel inverters, including operation in overmodulation range, IEEE Trans. Power Electron. 22 (2) (2007) 517–526.
  • [8] M. A. S. Aneesh, A. Gopinath, M. R. Baiju, A simple space vector PWM generation scheme for any general n-level inverter, IEEE Trans. Ind. Electron. 56 (5) (2009) 1649–1656.
  • [9] N. Celanovic, D. Boroyevich, A fast space-vector modulation algorithm for multilevel three-phase converters, IEEE Trans. Ind. Appl. 37 (2) (2001) 637–641.
  • [10] Z. Shu, N. Ding, J. Chen, H. Zhu, X. He, Multilevel SVPWM with DC-link capacitor voltage balancing control for diode-clamped multilevel converter based STATCOM, IEEE Trans. Ind. Electron. 60 (5) (2013) 1884–1895.
  • [11] J. H. Seo, C. H. Choi, D. S. Hyun, A new simplified space–vector PWM method for three-level inverters, IEEE Trans. Power Electron. 16 (4) (2001) 545–550.
  • [12] J. J. R. Andina, M. J. Moure, M. D. Valdes, Features, design tools, and application domains of FPGAs, IEEE Trans. Ind. Electron. 54 (4) (2007) 1810–1823.
  • [13] D. Navarro, O. Lucia, L. A. Barragan, J. I. Artigas, I. Urriza, O. Jimenez, Synchronous FPGA-based high-resolution implementations of digital pulse-width modulators, IEEE Trans. Power Electron. 27 (5) (2012) 2515–2525.
  • [14] B. Alecsa, M. N. Cirstea, A. Onea, Multi-DSP and - FPGA-based fully digital control system for cascaded multilevel converters used in FACTS applications, IEEE Trans. Ind. Informat. 8 (3) (2012) 511–527.
  • [15] B. Alecsa, M. N. Cirstea, A. Onea, Simulink modeling and design of an efficient hardware-constrained FPGA-based PMSM speed controller, IEEE Trans. Ind. Informat. 8 (3) (2012) 554–562.
  • [16] L. Idkhajine, E. Monmasson, A. Maalouf, Fully FPGA-based sensorless control for synchronous AC drive using an extended Kalman filter, IEEE Trans. Ind. Electron. 59 (10) (2012) 3908–3918.
  • [17] H. F. Blanchette, T. O. Bachir, J. P. David, A state-space modeling approach for the FPGA-based real-time simulation of high switching frequency power converters, IEEE Trans. Ind. Electron. 59 (12) (2012) 4555–4567.
  • [18] M. P. Aguirre, L. Calvino, M. I. Valla, Multilevel currentsource inverter with FPGA control, IEEE Trans. Ind. Electron. 60 (1) (2013) 3–10.
  • [19] M. Curkovic, K. Jezernik, R. Horvat, FPGA-based predictive sliding mode controller of a three-phase inverter, IEEE Trans. Ind. Electron. 60 (2) (2013) 637–644.
  • [20] P. S. B. Nascimento, H. E. P. de Souza, F. A. S. Neves, L. R. Limongi, FPGA implementation of the generalized delayed signal cancelation-phase locked loop method for detecting harmonic sequence components in threephase signals, IEEE Trans. Ind. Electron. 60 (2) (2013) 645–658.
  • [21] M. Shahbazi, P. Poure, S. Saadate, M. R. Zolghadri, Faulttolerant five-leg converter topology with FPGA-based reconfigurable control, IEEE Trans. Ind. Electron. 60 (6) (2013) 5024–5031.
  • [22] K. Jezernik, J. Korelic, R. Horvat, PMSM sliding mode FPGA-based control for torque ripple reduction, IEEE Trans. Power Electron. 28 (7) (2013) 3549–3556.
  • [23] M. Shahbazi, P. Poure, S. Saadate, M. R. Zolghadri, FPGA-based reconfigurable control for fault-tolerant back-to-back converter without redundancy, IEEE Trans. Ind. Electron. 60 (8) (2013) 3360–3371.
  • [24] Z. Shu, J. Tang, Y. Guo, J. Lian, An efficient SVPWM algorithm with low computational overhead for three-phase inverters, IEEE Trans. Power Electron. 22 (5) (2007) 1797–1805.
  • [25] G. Oriti, A. L. Julian, Three-phase VSI with FPGA-based multisampled space vector modulation, IEEE Trans. Ind. Appl. 47 (4) (2011) 1813–1820.
  • [26] S. Pan, J. Pan, Z. Tian, A shifted SVPWM method to control DC-link resonant inverters and its FPGA realization, IEEE Trans. Ind. Electron. 59 (9) (2012) 3383–3391.
  • [27] Y. Y. Tzou, H. J. Hsu, FPGA realization of space-vector PWM control IC for three-phase PWM inverters, IEEE Trans. Power Electron. 12 (6) (1997) 953–963.
  • [28] H. Hu, W. Yao, Z. Lu, Design and implementation of three-level space vector PWM IP core for FPGAs, IEEE Trans. Power Electron. 22 (6) (2007) 2234–2244.
  • [29] O. Lopez, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, Multilevel multiphase space vector PWM algorithm, IEEE Trans. Ind. Electron. 55 (5) (2008) 1933–1942.
  • [30] O. Lopez, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, Multi-level multiphase space vector PWM algorithm with switching state redundancy, IEEE Trans. Ind. Electron. 56 (3) (2009) 792–804.
  • [31] J. Alvarez, O. Lopez, F. D. Freijedo, J. Doval-Gandoy, Digital parameterizable VHDL module for multilevel multiphase space vector PWM, IEEE Trans. Ind. Electron. 58 (9) (2011) 3946–3957.
  • [32] O. Lopez, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, Comparison of the FPGA implementation of two multilevel space vector PWM algorithms, IEEE Trans. Ind. Electron. 55 (4) (2008) 1537–1547.
  • [33] D. G. Holmes, T. A. Lipo, Pulse Width Modulation for Power Converters, Wiley, New York, 2003.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-32280d60-2f89-4283-b550-19a4aa1636fd
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