Influence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs

• Autorzy: Stefanucci C , Buccella P , Kayal M. , Sallese J.M.
• Języki publikacji: EN

Abstrakty

EN

Minority carriers diffusion in Smart Power ICs substrate can be simulated in standard spice-like software using the EPFL Substrate Model. This model is based on a parasitic substrate network extracted from the integrated circuit layout following a given meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing strategy on the accuracy of the model when compared to Technology Computer Aided Design (TCAD) simulations. A parasitic lateral BJT will be analyzed as two-dimensional case study with both spice-like and finite element simulations for the minority carriers diffusion. Using statistical analysis a linear model is developed to discover the main geometrical domains influencing the accuracy of the studied model.

Słowa kluczowe

EN

smart power; IC; substrate modeling; minority carriers diffusion; numerical simulations

PL

smart power; IC; modelowanie substratów; dyfuzja nośników mniejszościowych; symulacje numeryczne

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2014
• Tom: Vol. 5, nr 2
• Strony: 61--68
• Opis fizyczny: Bibliogr. 16 poz.

Twórcy

autor

Stefanucci C

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Buccella P

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Kayal M.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Sallese J.M.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

Bibliografia

• [1] B. Murari, F. Bertotti and G. Vignola, Smart Power ICs, 2nd ed., pp. 218-220,Springer-Verlag, Berlin, 2002.
• [2] M. Schenkel, P. Pfaeffli, S. Mettler,W. Reiner, W.D. Aemmer, “Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection”, Proceeding of the 30th European Solid-State Device Research Conference, pp. 600-603, September, 2000.
• [3] R. Zhu, V. Khemka, A. Bose, T. Roggenbauer, ”Substrate Majority Carrier-Induced NLDMOSFET Failure and Its Prevention in Advanced Smart Power IC Technologies”, IEEE Transactions on Device and Materials Reliability, Vol.6, no.3, pp.386-392, September, 2006
• [4] M. Kollmitzer, M. Olbrich, E. Barke, ”Analysis and modeling of minority carrier injection in deep-trench based BCD technologies”, 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp.245248, June, 2013.
• [5] M. Schenkel, P. Pfaeffli, W. Wilkening, D. Aemmer, W. Fichtner, ”TCAD Based Design Methodology for Substrate Current Control in Smart Power ICs”, Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2002.
• [6] F. Lo Conte, J. M. Sallese, M. Pastre, F. Krummenacher, M. Kayal, ”Global Modeling Strategy of Parasitic Coupled Currents Induced by Minority-Carrier Propagation in Semiconductor Substrates”, IEEE Transactions on Electron Devices, vol.57, no.1, pp.263-272, January, 2010.
• [7] F. Lo Conte, J. M. Sallese, M. Kayal, ”Modeling methodology of high voltage substrate minority and majority carrier injections”, Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.194-197, September, 2010.
• [8] R.L. Plackett and J.P. Burman, ”The Design of Optimum Multifactorial Experiments”, Biometrika, vol. 33, pp. 305-25, June, 1946.
• [9] C. Stefanucci, P. Buccella, M. Kayal, and J.M. Sallese, “Influence of enhanced contact doping to minority carriers diffusion”, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014.
• [10] D. K. J. Lin and N. R. Draper, ”Projection Properties of Plackett and Burman Designs”, Technometrics, vol. 34, pp. 423-428, 1992.
• [11] Synopsys Sentaurus Device, http://www.synopsys.com/Tools/TCAD/DeviceSimulation
• [12] Cadence Spectre Circuit Simulator, http://www.cadence.com/products/cic/spectre_circuit
• [13] G. E. P. Box, ”Non-Normality and Tests on Variances”, Biometrika, vol. 40, pp. 318-335, 1953.
• [14] G. E. Box, J. S. Hunter and W. G. Hunter, ”Statistics for Experimenters: Design, Innovation, and Discovery”, 2nd Edition. Wiley, 2005.
• [15] G. E. P. Box and J. S. Hunter, ”The 2k-p Fractional Factorial Designs Part II”, Technometrics, vol. 3, pp. 449-459, 1961.
• [16] D. Cunthbert, ”Use of Half-Normal Plots in Interpreting Factorial Two-level Experiments”, Technometrics, vol. 1, pp. 311-341, 1959.