High-performance FPGA Architecture for Data Streams Processing on Example of IPsec Gateway

• Autorzy: Korona M. , Skowron K. , Trzepinski M. , Rawski M.

Identyfikatory

DOI

10.24425/123532

• Języki publikacji: EN

Abstrakty

EN

In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity - IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.

Słowa kluczowe

EN

IPsec; FPGA; hardware implementation; data stream processing

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2018
• Tom: Vol. 64, No. 3
• Strony: 351--356
• Opis fizyczny: Bibliogr. 16 poz., rys., tab.

Twórcy

autor

Korona M.

• Institute of Telecommunications, Faculty of Electronics and Information Technology, Warsaw University of Technology, Poland

autor

Skowron K.

• Institute of Telecommunications, Faculty of Electronics and Information Technology, Warsaw University of Technology, Poland

autor

Trzepinski M.

• Institute of Telecommunications, Faculty of Electronics and Information Technology, Warsaw University of Technology, Poland

autor

Rawski M.

• Institute of Telecommunications, Faculty of Electronics and Information Technology, Warsaw University of Technology, Poland

Bibliografia

• [1] OpenWRT project webpage, IPsec performance, accessed 26.03.18, https://wiki.openwrt.org/doc/howto/vpn.IPsec.performance
• [2] strongSwan project webpage, accessed 26.03.18, https://www.strongswan.org/
• [3] Klassert Steffen, Parallelizing IPsec, https://www.strongswan.org/docs/Steffen Klassert Parallelizing IPsec.pdf, 2010.
• [4] Intel Corporation, Fast Multi-buffer IPsec Implementations on Intel Architecture Processors, 2012.
• [5] Cisco Systems, Inc., Cisco IPsec and SSL VPN Solutions Portfolio, 2008.
• [6] Juniper Networks, Security Products Comparison Chart, 2015.
• [7] Helion Technology Limited, IPsec ESP IP Core for FPGA – Product Brief, accessed 26.03.18, http://www.heliontech.com/ipsec.htm
• [8] Sangjin Han, Keon Jang, Kyoung Soo Park, Sue Moon, PacketShader: a GPU-accelerated Software Router, http://shader.kaist.edu/packetshader, 2010.
• [9] Mateusz Korona, Implementation of IPsec protocol suite using fieldprogrammable devices, bachelor thesis, 2015.
• [10] ARM, AMBA 4 AXI4-Stream Protocol Specification, 2010.
• [11] Frankel S., Glenn R., Kelly S., RFC-3602, The AES-CBC Cipher Algorithm and Its Use with IPsec, 2003.
• [12] Housley R., RFC-3686, Using Advanced Encryption Standard (AES) Counter Mode With IPsec Encapsulating Security Payload (ESP), 2004.
• [13] Krawczyk H., Bellare M., Canetti R., RFC-2104, HMAC: Keyed-Hashing for Message Authentication, 1997.
• [14] Eastlake D. 3rd, Jones P., RFC-3174, US Secure Hash Algorithm 1 (SHA1), 2001.
• [15] Eun-Hee Lee, Seok-Man Kim, Chungbuk National University, Design of High Speed SHA-1 Architecture Using Unfolded Pipeline for Biomedical Applications, accessed 26.03.18, http://www.iiis.org/CDs2009/CD2009SCI/SCI2009/PapersPdf/S231IM.pdf
• [16] ETSI, EN 302 307 v. 1.1.2, Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications, 2006.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).