Pipelined pseudo-random number generator with the efficient post-processing method

• Autorzy: Dąbal P.
• Języki publikacji: EN

Abstrakty

EN

This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based on the chaotic nonlinear model and pipelined data processing. We investigated PRBG built on the chaotic logistic map and frequency dependent negative resistances (FDNR). A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx. We verified output pseudo-random bit stream by standard statistical tests NIST SP800-22. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRBG implementation in the programmable SoC device. For PRBGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. By composing the output stream of 3 data channels in PRBG with FDNR element, we get the maximum throughput equal to 38.43 Gbps. That is significantly greater comparing to the chaotic PRBGs described so far.

Słowa kluczowe

EN

chaotic system; post-processing; pseudorandom number generation; system on chip

PL

systemy chaotyczne; przetwarzanie końcowe; generator liczb pseudolosowych; system-on-chip

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2015
• Tom: Vol. 6, nr 2
• Strony: 43--48
• Opis fizyczny: Bibliogr. 39 poz., rys., wykr.

Twórcy

autor

Dąbal P.

• Faculty of Electronics, Military University of Technology, Warsaw, Poland

Bibliografia

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