Analytical and experimental determination of the parasitic parameters in high-frequency inductor

• Autorzy: Zdanowski M. , Barlik R.

Identyfikatory

DOI

10.1515/bpasts-2017-0013

• Języki publikacji: EN

Abstrakty

EN

The paper presents the results of calculations, simulations, and measurements of parasitic capacitance of winding in ferrite inductor suitable for cooperating with 2 kW DC-DC boost converter built using SiC JFET transistors, operating with a switching frequency of 100 kHz. The inductor winding is made of litz wire in a two-layer configuration. The lumped model of inductor winding was adopted. The results of analytical calculations have been compared with the results obtained from experimental investigations based on the resonance effect.

Słowa kluczowe

EN

model of inductor circuit; interlayer capacitance; parallel resonance; litz wire; inductor winding; skin effect

PL

pojemność pośrednia; rezonans równoległy; cewka indukcyjna

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2017
• Tom: Vol. 65, nr 1
• Strony: 107--112
• Opis fizyczny: Bibliogr. 19 poz., tab., rys., wykr.

Twórcy

autor

Zdanowski M.

• Institute of Control and Industrial Electronics, Warsaw University of Technology, 75 Koszykowa St., 00-662 Warsaw, Poland

autor

Barlik R.

• Institute of Control and Industrial Electronics, Warsaw University of Technology, 75 Koszykowa St., 00-662 Warsaw, Poland

Bibliografia

• [1] A. Nakajima, M. Shimizu, and H. Ohashi, “Power loss limit in unipolar switching devices: Comparison between Si superjunction devices and wide-bandgap devices”, IEEE Transactions on Electron Devices 56 (11), 2652-2656 (2009).
• [2] M. Treu, E. Vecino, M. Pippan, O. Häberlen, G. Curatola, G. Deboy, M. Kutschak, and U. Kirchner, “The role of silicon, silicon carbide and gallium nitride in power electronics”, Proc. of IEEE International Electron Devices Meeting (IEDM), San Francisco, 7.1.1-7.1.4 (2012).
• [3] J. Millán, P. Godignon, X. Perpiñà, A. Pérez-Tomás, and J. Rebollo, “A survey of wide bandgap power semiconductor devices”, IEEE Trans. Power Electron. 29 (5), 2155-2163 (2014).
• [4] H. Jain, S. Rajawat, and P. Agrawal, “Comparision of wide band gap semiconductors for power electronics applications”, Proc. of International Conference on Recent Advances in Microwave Theory and Applications, Jaipur, 878-881 (2008).
• [5] J. Rabkowski, D. Peftitsis, and H.-P. Nee, “Silicon carbide power transistors: A new era in power electronics is initiated”, IEEE Ind. Electron. Mag. 6 (2), 17-26 (2012).
• [6] X. Gu, Q. Shui, C.W. Myles, and M.A. Gundersen, “Comparison of Si, GaAs, SiC and GaN FET-type switches for pulsed power applications”, Proc. of 14th IEEE International Pulsed Power Conference, Dallas, 362-365 (2003).
• [7] Y. Su, Q. Li, M. Mu, and F.C. Lee, “High frequency inductor design and comparison for high efficiency high density pols with gan device”, Proc. of Energy Conversion Congress and Exposition (ECCE), 2146-2152 (2011).
• [8] M. Biglarbegian, N. Shah, I. Mazhari, J. Enslin, and B. Parkhideh, “Design and evaluation of high current pcb embedded inductor for high frequency inverters”, Proc. of Applied Power Electronics Conference and Exposition (APEC), 2998-3003 (2016).
• [9] C. Liu, L. Qi, X. Cui, and X. Wei, “Experimental extraction of parasitic capacitances for high-frequency transformers”, IEEE Trans. on Power Electronics, (2016).
• [10] X. Liu, Y. Wang, J. Zhu, Y. Guo, G. Lei, and C. Liu, “Calculation of capacitance in high-frequency transformer windings”, IEEE Trans. on Magnetics 52 (7), (2016).
• [11] I. Josifović, J. Popović-Gerber, and J.A. Ferreira, “Improving SiC JFET switching behavior under influence of circuit parasitics”, IEEE Transactions on Power Electronics 27 (8), 3843-3854 (2012).
• [12] Z. Zhang, B. Guo, F. Wang, L.M. Tolbert, B.J. Blalock, Z. Liang, and P. Ning, “Impact of ringing on switching losses of wide bang-gap devices in a phase-leg configuration”, Proc. of Twenty- Ninth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Fort Worth, 2542-2549 (2014).
• [13] M. Zdanowski, J. Rąbkowski, K. Kostov, and H.P. Nee, “The role of the parasitic capacitance of the inductor in boost converters with normally-on SiC JFETs”, Proc. of 7th International Power Electronics and Motion Control Conference (IPEMC), Harbin, 1842-1847 (2012).
• [14] M. Zdanowski, K. Kostov, J. Rąbkowski, R. Barlik, and H.P. Nee, “Design and evaluation reduced self-capacitance inductor in DC-DC converters with fast-switching SiC transistors”, IEEE Trans. On Power Electronics 29 (5), 2492-2499 (2014).
• [15] M. Zdanowski, “High-frequency DC-DC interleaved boost converter with SiC devices and magnetic components with reduced parasitic capacitance”, PhD dissertation, Warsaw University of Technology, Faculty of Electrical Engineering, Warsaw, (2015), [in Polish].
• [16] K. Gorecki and K. Detka, “The parameter estimation of the electrothermal model of inductors”, Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials 45 (1), 29-38 (2015).
• [17] S. Weber, M. Schinkel, S. Guttowski, W. John, and H. Reichl, “Calculating parasitic capacitance of three-phase common-mode chokes”, Proc. of PCIM, Nuremberg, (2005).
• [18] E.C. Snelling, Soft Ferrites - Properties and Applications, Ilife Books LTD, 1969.
• [19] V.C. Valchev, and A. Van den Bossche, Inductors and Transformers for Power Electronics, CRC Press Taylor & Francis Group, LLC, 2005.

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).