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FIRV: A language-based control flow integrity protection for RISC-V architectures

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Warianty tytułu
PL
FIRV: oparta na języku ochrona integralności przepływu sterowania dla architektur RISC-V
Języki publikacji
EN
Abstrakty
EN
Side-channel and fault-injection attacks using e.g. EM/laser pulse, power glitching are a major concern in the context of embedded systems, IoT devices, and cloud security. The Software-implemented Hardware-fault Tolerance (SIHFT) countermeasures are the main approach to hardening the systems built using Commercial Off-the-Shelf (COTS) components, in which modification of hardware is not feasible. The research presented in this article is focused on an open-source solution to language-based, compile-time application of SIHFT countermeasures. The proof-of-concept implementation is based on the LLVM compiler framework and demonstrates using Rust language frontend, allowing the use of other compiler features, like optimisation passes and support for multiple target platforms. The results of the research are publicly available in GitHub repository.
PL
Ataki kanałem pobocznym I wstrzykiwanie błędów przy użyciu impulsu elektromagnetycznego/laserowego, lub usterki zasilania, stanowią poważny problem w kontekście systemów wbudowanych, urządzeń IoT i bezpieczeństwa w chmurze. Implementowane programowo środki zaradcze Hardware-Fault Tolerance (SIHFT) są głównym podejściem do utwardzania systemów zbudowanych przy użyciu komercyjnych komponentów, w których modyfikacja sprzętu nie jest możliwa. Badania przedstawione w tym artykule koncentrują się na otwarto-zródłowym językowym rozwiązaniu stosowanym w czasie kompilacji. Implementacja prototypu jest oparta na projekcie modularnego kompilatora LLVM i demonstruje użycie kompilatora dla języka Rust, co pozwala na korzystanie z innych funkcji kompilatora, takich jak przebiegi optymalizacyjne i obsługa wielu platform docelowych. Wyniki badań są publicznie dostępne w repozytorium GitHub.
Rocznik
Strony
204--209
Opis fizyczny
Bibliogr. 39 poz., rys.
Twórcy
  • Wydział Informatyki i Telekomunikacji, Katedra Podstaw Informatyki, ul. Janiszewskiego 11/17, 50-372 Wrocław
  • Wydział Informatyki i Telekomunikacji, Katedra Podstaw Informatyki, ul. Janiszewskiego 11/17, 50-372 Wrocław
Bibliografia
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  • [16] Patterson D.A., Hennessy J.L., Computer Organization and Design RISC-V Edition: The Hardware Software Interface,Morgan Kaufmann Publishers Inc., (2017)
  • [17] Waterman A., Asanović K., The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213. Tech. rep., RISC-V Foundation, (2019)
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  • [25] Chen Z., et al., A compiler approach to mitigate fault attacks via enhanced simdization, In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC) (2017), 57–64
  • [26] Schilling R., Werner M., Mangard S., Securing conditional branches in the presence of fault attacks, In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). (2018), 1586–1591
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  • [29] Richter-Brockmann J., et al., Fiver - robust verification of countermeasures against fault injections, IACR Trans. on Cryptographic Hardware and Embedded Sys., (2021), 447–473
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  • [34] Geier J., et al., CompaSeC: A compiler-assisted securitycountermeasure to address instruction skip fault attacks on RISC-V, In 2023 28th Asia and South Pacific Design AutomationConference (ASP-DAC), (2023), 1–7
  • [35] Vankeirsbilck J., et al., Random additive signature monitoring for control flow error detection, IEEE Transactions on Reliability66(4) (2017), 1178–1192
  • [36] Dumont M., Lisart M., Maurine P., Electromagnetic fault injection: How faults occur, In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FTDC), (2019), 9-16
  • [37] Breier J., Hou X., How practical are fault injection attacks, really? IEEE Access, 10 (2022), 113122–113130
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  • [39] Wróbel Sz., Project FIRV, (2023), https://github.com/firv-comp
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-2d96c90e-1136-4f98-9bb5-0a5898b30b86
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