Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD audio amplifiers

• Autorzy: Kuta S. , Kołodziejski W. , Jasielski J.

Identyfikatory

DOI

10.5604/01.3001.0010.7555

• Języki publikacji: EN

Abstrakty

EN

The paper presents an original architecture and implementation of 9-bit LBDD hybrid DPWM circuit for Class-BD digital audio amplifier. The input PCM signals are directly transformed into 24-bit LBDD DPWM signals and then are requanized to the 9-bit digital outputs using noise-shaping process to support high fidelity with practical values of time resolution, and finally are converted by the DTCs into the two physical trains of 1-bit PWM signals. The architecture of the proposed Class-BD hybrid DPWM circuit is composed of two Class-AD ones. The hybrid quantizer converts 6 MSB bits using counter method, based on the STM32F407xx microcontroller, while the remaining 3 LSB bits - using a method based on the Programmable Tapped Delay Line (PTDL). All necessary time waveforms are generated on the base of the internal microcontroller oscillator 168 MHz. The proposed 9-bit Class-DB DPWM circuit allows to attain SNR of 110 dB and THD about 0,2% within the audio baseband, at switching frequency of 328.1 kHz, clock frequency of 42 MHz and modulation index M = 0.95. Basic verification of algorithm and circuit operation as well as simulation and preliminary experimental results have been performed.

Słowa kluczowe

EN

class-D digital audio amplifier; Digital Pulse Width Modulator (DPWM); Linearized Pulse Width Modulation (LPWM); Linearized Class-AD Double sided (LADD); Linearized Class-BD Double sided (LBDD); Programmable Tapped Delay Line (PTDL); Analog Delay Locked Loop (ADLL); Digital to Time Converter (DTC)

PL

cyfrowy wzmacniacz audio klasy D; modulator szerokości impulsu cyfrowego (DPWM); Linearized Pulse Width Modulation (LPWM); zlinearyzowana klasa AD dwustronna (LADD); Linearized Class-BD Double sided (LBDD); programowalna opóźniona linia opóźnienia (PTDL); pętla z opóźnieniem analogowym (ADLL); konwerter cyfrowo-czasowy (DTC)

• Wydawca: Państwowa Wyższa Szkoła Zawodowa w Tarnowie
• Czasopismo: Science, Technology and Innovation
• Rocznik: 2017
• Tom: Vol. 1, no. 1
• Strony: 1--10
• Opis fizyczny: Bibliogr. 20 poz., rys.

Twórcy

autor

Kuta S.

• State Higher Vocational School in Tarnow, Mickiewicza 8, 33-100 Tarnów, Poland

autor

Kołodziejski W.

• State Higher Vocational School in Tarnow, Mickiewicza 8, 33-100 Tarnów, Poland

autor

Jasielski J.

• State Higher Vocational School in Tarnow, Mickiewicza 8, 33-100 Tarnów, Poland

Bibliografia

• 1. M. Berkhout, L. Dooper, IEEE Transactions On Circuits And Systems-I: Regular Papers, 2010, 57, 991–1002.
• 2. R. Cellier, G. Pillonnet, A. Nagari, N. Abouchi, An Review of Fully Digital Audio Class D Amplifiers Topologies, Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop, June 28-July 1, 2009.
• 3. Ch. Morrison, S. Weiss, M. Macleod and R. Stewart, Comparison of Single- and Double-Sided Pulse Width Modulated Signals with Non-Linear Predistortion, Proceedings of the 5th European DSP Education and Research Conference, 2012, Amsterdam.
• 4. S.M. Munk, K.S. Andersen, State of the Art Digital Pulse Modulated Amplifier System, AES 23rd Int. Conf, Copenhagen, Denmark, 2003 May 23–25.
• 5. C. Pascual, Z. Song, P.T. Krein, et. al., IEEE Transactions on Power Electronics, 2003, 18, 474–485.
• 6. M. Johansen, K. Nielsen, A Review and Comparison of Digital PWM Methods for Digital Pulse Modulation Systems, 107th AES Convention, 1999 September 24-27, New York.
• 7. F. Guanziroli, R. Bassoli, C. Crippa, D. Devecchi, and G. Nicollini., IEEE Journal Of Solid-State Circuits, 2012, 47, 686–698.
• 8. Luo Shumeng and Li Dongmei, Journal of Semiconductors, 2013, 34, 115001-1–115001-6.
• 9. L. Dooper, M. Berkhout, IEEE Journal Of Solid-State Circuits, 2012, 47, 1524–1534.
• 10. Jia-Ming Liu, Shih-Hsiung Chien, Tai-Haur Kuo, IEEE Journal Of Solid-State Circuits, 2012, 47, 1344–1354.s
• 11. B.H. Gwee, J.S. Chang, H. Li, IEEE Transactions On Circuits And Systems -Ii: Analog and Digital Signal Processing, 2002, 49, 245–2256.
• 12. A. Syed, E. Ahmed, D. Maksimovic, E. Alarcon, Proc. IEEE Power Electron. Spec. Conf., 2004, 6, 4689–4695.
• 13. B.J. Patella, A. Prodic´, A. Zirger, D. Maksimovic´, IEEE Transactions on Power Electronics, 2003, 18, 438–446.
• 14. Xuzhen Shen, Xiaobo Wu, and Jing Lu, Lin Qin, Proceedings of the International MultiConference of Engineers and Computer Scientists, 2010, Vol II, IMCS 2010, March 2010.
• 15. J. Jasielski, S. Kuta, W. Machowski, W. Kołodziejski, Microelectronics Journal, 2014, 45, 1202 – 1211.
• 16. J. Jasielski, S. Kuta, W. Machowski, W. Kołodziejski, „Hybrid LBDD PWM Modulator for Digital Class-BD Audio Amplifier Based on STM32F407VGT6 Microcontroller and Analog DLL”, Mixed Design of Integrated Circuits & Systems (MIXDES), 2015 Proceedings of the 22st International Conference, 25-27 June 2015.
• 17. J. Jasielski, W. Kołodziejski, S. Kuta, W. Machowski; “An Analog Dual Delay Locked Loop Using Coarse and Fine Programmable Delay Elements”, Proceedings of the 20-th International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), 2013, Gdynia, Poland, June, Pgs. 20–22.
• 18. RM0090 Reference manual. STM32F40xxx, STM32F41xxx, STM32F42xxx, STM32F43xxx advanced ARM-based 32-bit MCUs.
• 19. STM32F405xx STM32F407xx, Datasheet, June 2013, DocID022152 Rev 4.
• 20. UM1472 User manual Discovery kit for STM32F407/417 lines, January 2014 DocID022256 Rev 4.