PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Powiadomienia systemowe
  • Sesja wygasła!
  • Sesja wygasła!
  • Sesja wygasła!
Tytuł artykułu

A New Approach to the Design of Low-Complexity Direct Digital Frequency Synthesizer

Wybrane pełne teksty z tego czasopisma
Identyfikatory
Warianty tytułu
PL
Nowe podejście do projektowania bezpośredniego syntezatora cyfrowego o małej złożoności
Języki publikacji
EN
Abstrakty
EN
A low–complexity direct digital frequency synthesizer based on linear interpolation method is presented in this paper. The proposed architecture employs a new technique to derive the slope coefficients at the first sample of each segment's interval thereby eliminating the ROM which stores those values. ROM elimination has resulted in significant logic element saving and simplified the whole DDFS structure. The proposed DDFS has been analyzed using MATLAB and tested over entire Nyquist frequency range. The spurious free dynamic range (SFDR) of synthesized sinusoid achieved is 84 dBc. The resultant low complexity architecture along with high spectral purity synthesized signal meets the specifications of recent portable battery-driven products.
PL
W artykule przedstawiono bezpośredni syntezator cyfrowy częstotliwości, opracowany w oparciu o metodę interpolacji liniowej. Zastosowana technika pozwala na uzyskanie współczynnika pochyłości już z pierwszą próbką każdego z interwałów segmentów, przez co eliminowana jest konieczność użycia pamięci ROM. Przeprowadzono symulacje proponowanego rozwiązania w pełnym zakresie częstotliwości Niquist’a. Działanie metody zostało porównane z innymi znanymi architekturami.
Rocznik
Strony
157--160
Opis fizyczny
Bibliogr. 18 poz., rys.
Twórcy
autor
  • University of Kebangsaan Malaysia
autor
  • University of Kebangsaan Malaysia
autor
  • University of Kebangsaan Malaysia
Bibliografia
  • [1] Lai Lin-hui, Li Xiao-jin. & Lai Zong-Sheng. (2008). A Low Complexity Direct Digital Frequency Synthesizer, In: Proceedings of IEEE 9th International Conference on Solid- State and Integrated-Circuit Technology (pp. 1653 – 1656).
  • [2] Nicholas, H.T. & Samueli, H. (1987). An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase Accumulator Truncation, In: Proceedings of IEEE International Conference on Frequency Control Symposium (pp.495–502).
  • [3] Shiung, D. & Huei-Wen, Ferng. (2004). An Economical Frequency Synthesizer Using Interpolation Techniques, In: Proceedings of IEEE International Conference on Vehicular Technology (pp. 3857–3860).
  • [4] Dayu, Y. & Dai, F.F. (2004). A 10Ghz Nonlinear Cosine-Weighted Digital-to-Analog Converter for High-Speed Direct Digital Synthesis, In: Proceedings of IEEE International Conference on Silicon Monolithic Integrated Circuits in RF Systems ( pp. 73–76).
  • [5] Hai, U., Khan, M.N., Imran, M.S. & Rehan, M. (2005). Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture, In: Proceedings of IEEE International Conference on Microelectronics (pp. 36–39).
  • [6] Sodagar, A.M. & Lahiji, G.R.(2000). Second-order Parabolic Approximation: A New Mathematical Approximation Dedicated to ROM-Less DDFSs, In: Proceedings of IEEE International Conference on Microelectronics ( pp. 47–50).
  • [7] Sodagar, A.M. & Lahiji, G.R. (2001). A pipelined ROM-Less Architecture for Sine-output Direct Digital Frequency Synthesizers Using the Second-order Parabolic Approximation, IEEE Transactions on Circuits and Systems, Part II- Analog and Digital Signal Processing 48,850–857.
  • [8] Strollo, A.G, Napoli, E. & De Caro, D. (2002).‘Direct Digital Frequency Synthesizers Using First-order Polynomial Chebyshev Approximation, In: Proceedings of IEEE International Conference on Solid State Circuits (pp. 527–530).
  • [9] Madisetti, A., Kwentus, A.Y. & Willson, A.N. (1995).A Sine/Cosine Direct Digital Frequency Synthesizer Using an Angle Rotation Algorithm,In: Proceedings of IEEE International Conference on Solid State Circuits ( pp. 262–263).
  • [10] Madisetti, A., Kwentus, A.Y. & Willson, A.N. (1999).A 100-Mhz, 16-b, Direct Digital Frequency Synthesizer with A 100-dBc Spurious-Free Dynamic Range. IEEE Transactions on Solid- State Circuits34, 1034–1043.
  • [11] De Caro, D. & Strollo, A.G. (2005). High-Performance Direct Digital Frequency Synthesizers Using Piecewise-Polynomial Approximation. IEEE Transactions on Circuit and Systems 52,324–336.
  • [12] Chen, Y.H. & Chau, Y.A. (2010). A Direct Digital Frequency Synthesizer Based on a New Form of Polynomial Approximations. IEEE Transactions on Consumer Electronics 56,436–440.
  • [13] Nicholas, H.T., Samueli, H. & and Kim, B. (1988). The Optimization of Direct Digital Frequency Synthesizer Performance in the Presence of Finite Word Length Effects, In: Proceedings of IEEE International Conference on Frequency Control Symposium (pp. 357–363).
  • [14] Freeman, R.A. (1989). Digital Sine Conversion Circuit for Use in Direct Digital Synthesizers. U.S. Patent No.4 809 205.
  • [15] Liu, S-I., Yu, T-B. & Tsao, H-W. (2001). Pipeline Direct Digital Frequency Synthesizer Using Decomposition Method. IET J on Circuit, Devices, and Systems148, 141–144.
  • [16] Chimakurthy. L.S.J., Ghosh, M., Dai, F.F. & Jaeger, R.C. (2006).A Novel DDS Using Nonlinear ROM Addressing with Improved Compression Ratio and Quantization Noise. IEEE Transactions on Ultrasonic, Ferroelectric and Frequency Control 53,274–283.
  • [17] Kroupa, V.F. (1999). Direct Digital Frequency Synthesizers. Piscataway. NJ: IEEE Press.
  • [18] Langlois, J.M.P. & Al-Khalili, D. (2003). Novel Approach to the Design of Direct Digital Frequency Synthesizers Based on Linear Interpolation. IEEE Transactions on Circuit and Systems, Part II 50,567–578.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-263b3ea2-a245-4748-9e61-69f50a196e05
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.