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With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.
Rocznik
Tom
Strony
307--312
Opis fizyczny
Bibliogr. 33 poz., il.
Twórcy
autor
- Department of Electronics and Communication Engineering, C. Abdul Hakeem College of Engineering and Technology, Melvisharam, Tamil Nadu, India
autor
- Department of Electronics and Communication Engineering, C. Abdul Hakeem College of Engineering and Technology, Melvisharam, Tamil Nadu, India
autor
- Department of Electronics and Communication Engineering, C. Abdul Hakeem College of Engineering and Technology, Melvisharam, Tamil Nadu, India
Bibliografia
- [1] C. Ryu, “Microstructure and reliability of copper interconnects,” Ph.D. dissertation, Stanford University, 1998.
- [2] “International technology roadmap for semiconductors (ITRS),” 2003.
- [3] H. B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
- [4] V. Adler and E. G. Friedman, “Repeater design to reduce delay and power in resistive interconnect,” IEEE Transactions on Circuits Systems II, Analog Digital Signal Processing, vol. 45, no. 5, pp. 607-616, May 1998.
- [5] A. Nalamalpu, S. Srinivasan, and W. P. Burleson, “Boosters for driving long onchip interconnects-Design issues, interconnect synthesis, and comparison with repeaters,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 21, no. 1, pp. 50-62, January 2002.
- [6] J. Lillis, C.-K. Cheng, and T.-T. Y. Lin, “Optimal and Efficient Buffer Insertion and Wire Sizing,” IEEE Custom Integrated Circuits Conference, pp. 259-262, 1995.
- [7] C. J. Alpert, A. Devgan, and S. T. Quay, “Buffer insertion with accurate gate and interconnect delay computation,” in DAC, June 1999.
- [8] C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” IEEE Transactions on CAD, vol. 22, no. 5, May 2003.
- [9] M. A. El-Moursy and E. G. Friedman, “Optimum Wire Tapering for Minimum Power Dissipation in RLC Interconnects,” Department of Electrical and Computer Engineering University of Rochester, New York.
- [10] E. G. Friedman and M. A. El-Moursy, “Wire shaping of RLC interconnects,” Integration, the VLSI Journal, vol. 40, no. 4, pp. 461-472, July 2007.
- [11] R. Bashirullah, W. Liu, and R. K. Cavin, “Current-mode signaling in deep submicrometer global interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 406-417, June 2003.
- [12] S. Mishra, P. Agnihotry, and B. K. Kaushik Divya Mishra, “Effect of Distributed Shield Insertion on Crosstalk in Inductively Coupled VLSI Interconnects,” Journal of Computer Science and Engineering, vol. 1, no. 1, May 2010.
- [13] J. Zhang and E. G. Friedman, “Effect of shield insertion on reducing crosstalk noise between coupled interconnects,” Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 2, pp. 529-532, 23-26 May 2004.
- [14] L. Qiao, “Shielding Methodologies for VLSI Interconnect,” Department of Electrical and Computer Engineering University of Rochester.
- [15] A. Maheshwari and W. Burleson, “Differential current-sensing for onchip interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 12, pp. 1321–1329, December 2004.
- [16] N. Tzartzanis and W. W. Walker, “Differential current-mode sensing for efficient on-chip global signaling,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp. 2141–2147, November 2005.
- [17] M. Yamashina and H. Yamada, “MOS current mode logic MCMLcircuit for low-power GHz processors,” NEC Research and Development, vol. 36, no. 1, pp. 54-63, January 1995.
- [18] E. Seevinck, P. J. van Beers, and H. Ontrop, “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM’s,” IEEE Journal of Solid-State Circuits, pp. 525-536, 1991.
- [19] M. Dave, M. S. Baghini, and D. Sharma, “Current mode interconnect,” Department Of Electrical Engineering, Indian Institute Of Technology, Bombay, 2 December 2010.
- [20] M. W. Allam and M. I. Elmasry, “Dynamic current mode logic (Dy-CML): a new low-power high-performance logic style,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 550–558, March 2001.
- [21] L. Zhang, J. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. Franzon, “Driver pre-emphasis techniques for on-chip global buses,” in Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 8-10 August 2005, pp. 186-191.
- [22] A. Maheshwari, “Circuit and Signaling Techniques for on-chip interconnects,” Ph.D. dissertation, Circuit and Signaling Techniques for on-chip interconnects, 2004.
- [23] V. Venkatraman and W. Burleson, “Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations,” in Sixth International Symposium on Quality of Electronic Design, 2005.
- [24] Impact of Process Variations on Multi-level Signaling for On-Chip Interconnects, in Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005.
- [25] E. Nigussie, T. Lehtonen, S. Tuuna, J. Plosila, and J. Isoaho, “Research Article: High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling,” Hindawi Publishing Corporation VLSI Design, p. 13, 2007, Article ID 46514.
- [26] I. Dhaou, V. Sundarajan, H. Tenhunen, and K. Parhi, “Energy efficient signaling in deep sub-micron ICs,” IEEE International Conference on Symposium on Quality Electronic Design, pp. 319–324, March 2001.
- [27] S. Srinivasan, “Circuit and signaling strategies for On-Chip Global Interconnects in DSM CMOS,” Master’s thesis, The Department of ECE, University of Massachusetts, Amherst, 2002, chapters 3-4.
- [28] H. C. Kirsch and E. Ku, “Multiple-bit current-mode data bus,” February 2001, US Patent Number 6184714.
- [29] Multiple-bit current-mode data bus, August 2001, US Patent Number 6255067.
- [30] T. Maekawa, S. Amakawa, H. Ito, N. Ishihara, and K. Masu, Highly Energy-Efficient On-Chip Pulsed-Current-Mode Transmission Line Interconnect, Solid State Circuits Technologies. InTech, 2010, J. W. Swart (Ed.).
- [31] A. P. Jose, G. Patounakis, and K. L. Shepard, “Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication,” IEEE Journal Of Solid-State Circuits, vol. 41, no. 4, April 2006.
- [32] R. Bashirullah, W. Liu, R. Cavin, and D. Edwards, “A Hybrid Current/Voltage Mode On-Chip Signaling Scheme With Adaptive Bandwidth Capability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, August 2004.
- [33] J. M. Wilson, R. Bashirullah, and L. Zhang, “A 32-Gb/s On-Chip Bus with Driver Pre-Emphasis Signaling,” IEEE Transactions on Very Large Scale Intergration Systems, vol. 17, no. 9, p. 1267, September 2009.
Typ dokumentu
Bibliografia
Identyfikator YADDA
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