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Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

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Języki publikacji
EN
Abstrakty
EN
Leakage power is the dominant source of power dissipation in nanometer technology. As per the International Technology Roadmap for Semiconductors (ITRS) static power dominates dynamic power with the advancement in technology. One of the well-known techniques used for leakage reduction is Input Vector Control (IVC). Due to stacking effect in IVC, it gives less leakage for the Minimum Leakage Vector (MLV) applied at inputs of test circuit. This paper introduces Particle Swarm Optimization (PSO) algorithm to the field of VLSI to find minimum leakage vector. Another optimization algorithm called Genetic algorithm (GA) is also implemented to search MLV and compared with PSO in terms of number of iterations. The proposed approach is validated by simulating few test circuits. Both GA and PSO algorithms are implemented in Verilog HDL and the simulations are carried out using Xilinx 9.2i. From the simulation results it is found that PSO based approach is best in finding MLV compared to Genetic based implementation as PSO technique uses less runtime compared to GA. To the best of the author’s knowledge PSO algorithm is used in IVC technique to optimize power for the first time and it is quite successful in searching MLV.
Twórcy
  • G.V.P. College of Engineering (Autonomous), Department of ECE, Visakhapatnam, AP, India
  • JNTUH College of Engineering, Department of ECE, Hyderabad, Telangana, India
Bibliografia
  • [1] Ing-Chao-Lin, Chin-Hong-Lin, Kuan-Hui-Li, “Leakage and aging optimization using Transmission gate based technique”, IEEE Transactions on Computer aided design of integrated circuits and systems, vol. 32, No. 1, Jan 2013.
  • [2] Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Sub micrometer CMOS Circuits,” PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003.
  • [3] Se Hun Kim, Vincent J. Moone, “Sleepy keeper:a New Approach to Low-leakage Power VLSI Design,” VLSI SOC conference, PP. 367-372, 2006.
  • [4] Jun Cheol Park and Vincent J. Moone III , “Sleepy Stack Leakage Reduction”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 14, No. 11, pp. 1250-1263, November 2006.
  • [5] Farzan Fallah, Massoud Pedram “Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits” in IEICE Transactions, pp. 509-519, 2005.
  • [6] Zhanping Chen, Liqiong Wei, Mark Johnson, Kaushik Roy, “Estimation of standby leakage power in CMOS circuits considering Accurate modeling of Transistor stacks”, ACM transactions, international symposium on Low power electronics and design, ISLPED, pp. 239-244, 1998.
  • [7] Nikhil Jayakumar, Sunil P Khatri,“An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification”, IEEE Design Automation conference, DATE07, 2007.
  • [8] Wei Wang, Yu Hu, Yin-He Han, Xiao-Wei Li, You Sheng Zhang, “Leakage current optimizations during test based on don’t care bits assignments”, Journal of computer science and technology, pp. 673-680, Sep 2007.
  • [9] Lin Yuan, Gang Qu, “ A combined gate replacement and input vector control approach for leakage current reduction” , IEEE transactions on very large scale integration (vlsi) systems, vol. 14, no. 2, february 2006
  • [10] Afsin Abdollahi, Farzan Fallah, Massoud Pedram, “Leakage current reduction in CMOS vlsi circuits by input vector control”, IEEE transactions on very large scale integration (vlsi) systems, vol. 12, no. 2, february 2004.
  • [11] V. Leela Rani, M. Madhavi Latha, “Implementation of genetic algorithm for minimum leakage vector in input vector control approach”, IEEE conference,SPACES, Jan 2015.
  • [12] Zhanping Chen, Liqiong Wei, Mark Johnson, Kaushik Roy, “Estimation of standby leakage power in CMOS circuits considering Accurate modeling of Transistor stacks”, ACM transactions, international symposium on Low power electronics and design, ISLPED, pp. 239-244,1998.
  • [13] Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram, “Design of NBTI-resilient extensible processors”, INTEGRATION, the VLSI Journal, vol. 49, pp. 22-34, 2015.
  • [14] Abdoul Rjoub, Almotasem Belleah Alajlouni, Hassan Almanasrah, “A Fast input Vector Control Approach for subthreshold Leakage power reduction” , IEEE electro technical international conference,MELECON, 2012.
  • [15] Mourad Fakhfakh, Yann Cooren, Amin Sallem, Mourad Loulou, Patrick Siarry, “Analog circuit design optimization through the particle swarm optimization technique”, Analog Integrated Circuits and Signal processinh, vol. 63, pp.71-82, Springer, 2010.
  • [16] James Kennedy, Russell Eberhart, “Partcle Swarm Optimization”, IEEE international conference, 1995.
  • [17] Christopher W. Cleghorn, Andries P. Engelbrecht, “A generalized theoretical deterministic particle swarm model” , Swarm Intelligence, vol. 8, pp. 35-59, Springer,2014.
  • [18] Mohammad Reza Bonyadi, Zbigniew Michalewicz,“A locally convergent rotationally invariant particle swarm optimization algorithm”, Swarm Intelligence, vol. 8, pp.159-198, Springer, 2014.
  • [19] Xiaoying Zhao, Jiangfang Yi, Dong Tong, Xu Cheng, “Leakage power reduction for cmos combinational circuits”, IEEE international conference on solid state and integrated circuit technology, 2006.
  • [20] Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang, “SoC Leakage Power Reduction Algorithm by Input Vector Control”, IEEE international conference, 2005.
Uwagi
PL
Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-222a751a-d934-496d-ad59-d60ae01666ba
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