Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

• Autorzy: Shylu Sam D. S. , Sam Paul P. , Jeba Jingle Diana , Mano Paul P. , Samuel Judith , Reshma J. , Sudeepa P. Sarah , Evangeline G.

Identyfikatory

DOI

10.24425/ijet.2022.141275

Abstrakty

EN

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.

Słowa kluczowe

EN

flash ADC; low power; dynamic comparator; encoder

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2022
• Tom: Vol. 68. No. 3
• Strony: 565--570
• Opis fizyczny: Bibliogr. 21 poz., il., schem.

Twórcy

autor

Shylu Sam D. S.

• Karunya Institute of Technology & Sciences, Coimbatore, India

autor

Sam Paul P.

• Karunya Institute of Technology & Sciences, Coimbatore, India

autor

Jeba Jingle Diana

• Christ (Deemed to be University), Bangalore, India

autor

Mano Paul P.

• Alliance University, Bangalore, India

autor

Samuel Judith

• Karunya Institute of Technology & Sciences, Coimbatore, India

autor

Reshma J.

• Karunya Institute of Technology & Sciences, Coimbatore, India

autor

Sudeepa P. Sarah

• Karunya Institute of Technology & Sciences, Coimbatore, India

autor

Evangeline G.

• Karunya Institute of Technology & Sciences, Coimbatore, India

Bibliografia

• [1] S. Abdullah, Almansouri, Abdullah Alturki, Hossein Fariborzi, Khaled N. Salama and Talal Al-Attar “A 12.4fJ-FoM 4-bit flash ADC based on the strong ARM architecture.” IEEE 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2018. https://doi.org/10.1109/PRIME.2018.8430349
• [2] Mostafa M. Ayesh, Sameh Ibrahim, Mohamed M. Aboudina “A 15.5-mW 20-GSps 4-bit charge-steering flash ADC”, IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, https://doi.org/10.1109/MWSCAS.2015.7282153
• [3] D.S. Shylu, D. Jackuline Moni D. G. Nivetha, “Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications”, Wireless Personal Communication, Springer, vol.2, pp.657-678, 2016. https://doi.org/10.1007/s11277-016-3186-z
• [4] D.S. Shylu, D. Jackuline Moni, “Design of low power dynamic comparator with reduced kick back noise using clocked PMOS technique”, Journal of Electrical Engineering (JEE), vol.(3), pp.1-10, 2016.
• [5] D.S. Shylu, D. Jackuline Moni, “A 1.8V 22mW 10 bit 165 MSPS Pipelined ADC for Video Applications”, WSEAS Transactions on Circuits and systems, 13, pp.343-355, 2014.
• [6] Shahriar Shahramian Sorin, P. Voinigescu, Anthony Chan Carusone.“A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees” IEEE Journal of Solid-State Circuits, vol.6, pp.1709-1720, 2009. https://doi.org/10.1109/JSSC.2009.2020657
• [7] I. Kim, B. Sung, et al., “A 6 bit 4.1 GS/s Flash ADC with time domain latch interpolation in 90-nm CMOS,” IEEE J. Solid-State Circuits vol.6, pp. 1429–1441, 2013. https://doi.org/10.1109/JSSC.2013.2252516
• [8] Gregor Tretter, Moammad Mahdi Khafaji, et al., “Design and characterization of a 3-bit 24GS/s Flash ADC in 28-nm low power digital CMOS,” IEEE Trans. Microw. Theory Tech, vol. 4, pp.1143-1152, 2016. https://doi.org/10.1109/TMTT.2016.2529599
• [9] R. Oh, et al., “Power efficient flash ADC with complementary voltage to time converter,” Electron. Lett. Vol.12, pp.772-773, 2017. https://doi.org/10.1049/el.2017.1287
• [10] Mehdi Nasrollahpour, “Extra bit generation for high speed time based flash ADCs in 65nm CMOS”, IEEE International Symposium on Circuits and Systems (ISCAS), vol.1, 2018. https://doi.org/10.1109/ISCAS.2018.8351432
• [11] Hairong Yu and Mau-Chang Frank Chang. “A 1-v 1.25-GS/s 8-bit self calibrated flash ADC in 90 nm digital CMOS” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.(7), pp.668-672, 2008. https://doi.org/10.1109/TCSII.2008.921596
• [12] Jong-In Kim, Dong-Ryeol oh, et al., “A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC with cascaded latch interpolation,” IEEE J. Solid State Circuits, vol. 50, pp. 2319-2330, 2015. https://doi.org/10.1109/JSSC.2015.2460371
• [13] G.L. Madhumati, Mr. K. Ramakoteswara Rao, Dr. M. Madhavilatha “Comparison of 5-bit thermometer to binary decoders in 1.8v, 0.18um CMOS technology for flash ADCs”, Tehnicki Vjesnik , 22(6), pp.1425- 1431, 2015. https://doi.org/10.17559/TV-20130914070012
• [14] Jiangpeng Wanga, Wing-Shan Tam, Chi-Wah Kok & Kong-Pang Puna. "A 5-bit 500MS/s flash ADC with temperature-compensated inverter based comparator". Solid-State Electronics Letters, pp. 2(3):1-9, 2020. https://doi.org/10.1016/j.ssel.2020.01.007
• [15] Shylu, D.S.; Radha, S.; Paul, P. Sam; Sudeepa, Parakati Sarah (2019). “Design of low power 4-bit Flash ADC in 90nm CMOS Process”, [IEEE 2019 2nd International Conference on Signal Processing and Communication (ICSPC) - Coimbatore, India, pp.252–257, 2019. https://doi.org/10.1109/ICSPC46172.2019.8976538
• [16] C.-H. Chan, Y. Zu, et al., “A 5 bit 1.25GS/s 4 times capacitive folding flash ADC in 65 nm CMOS,” IEEE J. Solid State Circuits 48 (9), pp. 2154–2169, 2013. https://doi.org/10.1109/JSSC.2013.2264617
• [17] D. S. Shylu, Sam, J. Arolin, D. Jackuline Moni, “Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier,” International Conference on Circuits, Devices and Systems (ICDCS’18), pp.263-265, 2018. https://doi.org/10.1109/ICDCSyst.2018.8605152
• [18] D.S. Shylu, S. Jasmine, D. Jackuline Moni, “A Low Power Dynamic Comparator for a 12-bit Pipelined Successive Approximation Register (SAR) ADC” International Conference on Circuits, Devices and Systems (ICDCS’18), pp.339-342, 2018. https://doi.org/10.1109/ICDCSyst.2018.8605130
• [19] D.S. Shylu Sam, S. Radha, D. Jackuline Moni, P. Sam Paul, J. Jecintha, “Design of 1-V, 12-Bit Low Power Incremental Delta Sigma ADC for CMOS Image Sensor Applications,” International Journal of Recent Technology and Engineering (IJRTE) vol.7, no. 5S3, pp. 249-254, 2019.
• [20] D.S. Shylu, D. Jackuline Moni, P. Sam Paul, D. Nirmal, “A Novel architecture of 10-bit 40MSPS low power pipelined ADC using a simultaneous Capacitor and Op-amp sharing Technique,” Silicon, Springer, 14(3):1-9, 2022. https://doi.org/10.1007/s12633-021-01241-x
• [21] D.S. Shylu, P. Sam Paul “A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique,” Circuit World, 47(3), 274-283, 2021. https://doi.org/10.1108/CW-12-2020-0358

Uwagi

Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).