Digital-to-Time Converter for pulse train generation based on Look-Up Tables in FPGA

• Autorzy: Kwiatkowski P. , Różyc K. , Szplet R.
• Języki publikacji: EN

Abstrakty

EN

A Digital-to-Time Converter (DTC) is presented which allows to generate pulse train with resolution of 250 ps within 32 ns operation range. The converter is implemented in off-the-shelf Spartan-6 Field-Programmable Gate Array (FPGA) device, manufactured by Xilinx in 45 nm CMOS technology. The design is implemented with the use of Look-Up Tables (LUT) as delay elements. “Manual” Place and Route (P&R) process was involved to improve conversion linearity. Developed DTC can be used to improve the functionality of time interval generators.

Słowa kluczowe

EN

Digital-to-Time Converter; time interval generator; programmable delay line; programmable devices

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2018
• Tom: Vol. 64, No. 1
• Strony: 14--16
• Opis fizyczny: Bibliogr. 10 poz., rys., wykr.

Twórcy

autor

Kwiatkowski P.

• Military University of Technology, 2 Gen W. Urbanowicza St., 00-908 Warsaw, Poland

autor

Różyc K.

• Military University of Technology, 2 Gen W. Urbanowicza St., 00-908 Warsaw, Poland

autor

Szplet R.

• Military University of Technology, 2 Gen W. Urbanowicza St., 00-908 Warsaw, Poland

Bibliografia

• [1] Liu J. C., Huang C. J., Lee P. Y.: A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 4, pp. 621-629, 2018.
• [2] Kwiatkowski P., Różyc K., Sawicki M., Jachna Z., Szplet R.: 5 ps jitter programmable time interval/frequency generator. Metrol. Meas. Syst., vol. 24, no. 1, pp. 57-68, 2017.
• [3] Kwiatkowski P., Jachna Z., Różyc K., Kalisz J.: Accurate and low jitter time-interval generators based on phase shifting method. Rev. Sci. Instrum., vol. 83, no. 3, art. no. 034701, pp. 1-4, 2012.
• [4] Chen P., Chen P. Y., Lai J. S., Chen Y. J.: FPGA vernier digital-to-time converter with 1.58 ps resolution and 59.3 minutes operation range. IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, art. no. 5371812, pp. 1134-1142, 2010.
• [5] Chaberski D.: High-resolution time-interval generator. Przegląd Elektrotechniczny, vol. 2017, no. 10, pp. 25-32, 2017.
• [6] Giordano R. et al.: High-resolution synthesizable digitally-controlled delay lines. IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 3163-3171, 2015.
• [7] Kwiatkowski P., Szplet R.: Digital-to-time Converter with Pulse Train Generation Capability. Proc. 2018 IEEE Int. Instrum. Meas. Technol. Conf (I2MTC), Houston, TX, USA, 14-17 May 2018.
• [8] Szplet R., Sondej D., Grzęda G.: High-Precision Time Digitizer Based on Multiedge Coding in Independent Coding Lines. IEEE Trans. Instrum. Meas., vol. 65, no. 8, pp. 1884-1894, 2016.
• [9] Szplet R., Klepacki K.: An FPGA-Integrated Time-to-Digital ConverterBased on Two-Stage Pulse Shrinking. IEEE Trans.Instrum. Meas., vol. 59, no. 6, pp. 1663-1670, 2010.
• [10] Zhang J., Zhou D.: An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. IEEE Trans.Instrum. Meas., vol. 67, no. 2, pp. 406-414, 2017.

Uwagi

EN

1. This work has been supported by the Military University of Technology, Warsaw, Poland, as a part of the project PBS 661.

PL

2. Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).