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Partial reconfiguration exploration over P2IP architecture

Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
PL
Wykorzystanie strategii Partial Reconfiguration w architekturze P2IP
Języki publikacji
EN
Abstrakty
EN
P2IP is a real-time image and video processing architecture featuring reconfigurable runtime capabilities, low latency and high performance. However, low energy consumption and battery life are crucial when targeting portable devices. In some applications, not all processing elements are in use representing a power leak that a Partial Reconfiguration (PR) strategy could mitigate. To assess its impact, three image processing algorithms have been deployed in a variant of this architecture implemented in an FPGA. Measurements show that use of PR leads to energy savings of up to 45%.
PL
P2IP jest metoda przetwarzania obrazu i video w czasie rzeczywistym z dobrą jakością i małym opóźnieniem. W celu zmniejszenia poboru mocy opracowano strategię Partial Reconfiuguration PR oraz opracowano architekturę wykorzystując FPGA.
Rocznik
Strony
258--262
Opis fizyczny
Bibliogr. 18 poz., rys., tab.
Twórcy
autor
  • Federal Institute of Education, Science and Technology of Rio Grande do Norte, RN120 - Alto de Santa Luzia, Nova Cruz/RN, Brazil
autor
  • Department of Electrical Engineering, Federal University of Rio Grande do Norte, Natal/RN, Brazil
autor
  • Department of Electronics and Microelectronics, University of Mons, Mons, Belgium
  • Department of Electronics and Microelectronics, University of Mons, Mons, Belgium
autor
  • Department of Electronics and Microelectronics, University of Mons, Mons, Belgium
Bibliografia
  • [1] P. Possa, S. Mahmoudi, N. Harb, C. Valderrama and P. Manneback, “A multi-resolution FPGA-based architecture for realtime edge and corner detection”, IEEE Transactions on Computers, 63(10), pp. 2376-2388, 2014.
  • [2] P. Possa, N. Harb, E. Dokladalova and C. Sakuyama, “P2IP: A novel low-latency Programmable Pipeline Image Processor”, Microprocessors and Microsystems, 39(7), pp. 529-540, 2015.
  • [3] P. Possa, “Reconfigurable low-latency architecture for realtime image and video processing”, UMONS, Jun 2013.
  • [4] N. Nayak, “Accelerated Computation using Runtime Partial Reconfiguration”, University of Stuttgart, Nov 2013.
  • [5] S. Liu, R. Pittman and A. Forin, “Energy Reduction with Run- Time Partial Reconfiguration”, Microsoft Research, 2009.
  • [6] S. Liu, R. Pittman and A. Forin, “Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller”, Microsoft Research, 2009.
  • [7] T. Becker, W. Luk and P. Cheung, “Energy-aware optimization for run-time reconfiguration, 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)”, pp. 55-62, 2010.
  • [8] A. Ahmad, A. Amira, P. Nicholl and B. Krill, “Dynamic Partial Reconfiguration of 2-D HaarWavelet Transform (HWT) for face recognition systems, IEEE 15th International Symposium on Consumer Electronics”, pp. 9-13, 2011.
  • [9] A. Ihsen, “Design of Self-Tuning Reliable Embedded Systems and its Application in Railway Transportation Systems”, Université de Valenciennes, Apr 2016.
  • [10] J. Dondo, J. Barba, F. Rincón, F. Moya and J. López, “Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs”, Journal of Systems Architecture, 65(5), pp. 1484-1493, 2016.
  • [11] Xilinx, “Vivado Design Suite Tutorial - Partial Reconfiguration”, UG947, 2015.
  • [12] M. Kadi, P. Rudolph, D. Gohringer and M. Hubner, “Dynamic and partial reconfiguration of Zynq 7000 under Linux”, 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, pp. 1-5, 2013.
  • [13] B. Blodget, C. Bobda, M. Hubner and A. Niyonkuru, “Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs”, Field Programmable Logic and Application: 14th International Conference, FPL 2004 Proceedings, pp. 801-810, 2004.
  • [14] Xilinx, “ZC702 Evaluation Board for the Zynq-7000 XC7Z020 All Programmable SoC User Guide”, UG850, 2015.
  • [15] E. Srikanth, “Zynq-7000 AP SoC Low Power Techniques part 3 - Measuring ZC702 Power with a Standalone Application Tech Tip”, 2014.
  • [16] Texas Instruments, “USB Interface Adapter Evaluation Module User’s Guide”, 2006.
  • [17] J. Nunez-Yanez, M. Hosseinabady and A. Beldachi, “Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling”, IEEE Transactions on Computers, 59(1), pp. 1-15, 2013.
  • [18] Xilinx, “Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices”, 2013. 262
Uwagi
Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-2055bffc-a951-4cde-a2aa-c0e98871732e
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