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Języki publikacji
Abstrakty
The paper deals with fault diagnosis of nonlinear analogue integrated circuits. Soft spot short defects are analysed taking into account variations of the circuit parameters due to physical imperfections as well as self-heating of the chip. A method enabling to detect, locate and estimate the value of a spot defect has been developed. For this purpose an appropriate objective function was minimized using an optimization procedure based on the Fibonacci method. The proposed approach exploits DC measurements in the test phase, performed at a limited number of accessible points. For illustration three numerical examples are given.
Słowa kluczowe
Czasopismo
Rocznik
Tom
Strony
239--250
Opis fizyczny
Bibliogr. 28 poz., rys., tab., wykr., wzory
Twórcy
autor
- Lodz University of Technology, Faculty of Electrical, Electronic, Computer and Control Engineering, Stefanowskiego 18/22, 90-924 Łódź, Poland
autor
- Lodz University of Technology, Faculty of Electrical, Electronic, Computer and Control Engineering, Stefanowskiego 18/22, 90-924 Łódź, Poland
Bibliografia
- [1] Aminian, F., Aminian, M. (2001). Fault diagnosis of analog circuits using bayesian neural networks with wavelet transform as preprocessor. Journal of Electronic Testing: Theory and Applications, 17, 29‒36.
- [2] Aminian, M., Aminian, F. (2007). A modular fault-diagnosis system for analog electronic circuits using neural networks with wavelet transform as a preprocessor. IEEE Trans. Instrum. Meas., 56, 1546‒1554.
- [3] Catelani, M., Fort, A. (2002). Soft fault detection and isolation in analog circuits: some results and a comparison between a fuzzy approach and radial basis function networks. IEEE Trans. Instrum. Measur., 51, 196‒202.
- [4] Czaja, Z. (2013) Self-testing of analog parts terminated by ADCs based on multiple sampling of time response. IEEE Trans. Instrum. Measur., 62, 3160‒3167.
- [5] El-Gamal, M., Mohamed, M.D.A. (2007). Ensembles of neural networks for fault diagnosis in analog circuits. J. Electron. Test., 23, 323−339.
- [6] Gizopoulos, D. (2006). Advances in electronic testing. Challenges and methodologies. Dordrecht: Springer.
- [7] Grzechca, D., Rutkowski, J. (2009). Fault diagnosis in analog electronic circuits - the SVM approach. Metrol. Meas. Syst., 16(4), 583‒598.
- [8] Gyvez, J.P., Di, C. (1992). IC defect sensitivity for footprint-type spot defect. IEEE Trans. Comput.-Aided Design Integr. Cir. Syst., 11, 638‒658.
- [9] Huang, K., Stratigopoulos, H.G., Mir, S., Hora, C., Xing, Y., Kruseman, B. (2012). Diagnosis of local spot defect is analog circuits. IEEE Trans. Instrum. Measur., 61, 2701‒2712.
- [10] Kabisatpathy, P., Barua, A., Sinha, S. (2005). Fault diagnosis of analog integrated circuits. Dordrecht: Springer.
- [11] Kim, B., Swaminathan, M., Chatterjee, M., Schimmel, D. (1997). A novel test technique for MCM substrates. IEEE Trans. Comp. Packag. Manufact. Technol., 20, 2‒12.
- [12] Long, B., Li, M., Wang, H., Tian, S. (2013). Diagnostics of analog circuits based on LS-SVM using time domain features. Cir. Syst. Signal Process., 32, 2683‒2706.
- [13] Maly, W., Strojwas, A.J., Director, S.W. (1986). VLSI yield prediction and estimation: a unified framework. IEEE Trans. Comput.-Aided Des. Integr. Cir. Syst., 5, 114‒130.
- [14] Materka, A., Strzelecki, M. (1996). Parametric testing of mixed-signal circuits by ANN processing of transient responses. Journal of Electronic Testing: Theory and Applications, 9, 187‒202.
- [15] Rodrigez-Montanes, R., de Gyves, J.P., Volf, P. (2002). Resistance characterization for weak open defects. IEEE Des. Test. Comput., 19, 18‒26.
- [16] Robotycki, A., Zielonko, R. (2002). Fault diagnosis of analog piecewise linear circuits based on homotopy. IEEE Trans. Instrum. Measur., 51, 876‒881.
- [17] Tadeusiewicz, M., Hałgas, S. (2015). A new approach to multiple soft fault diagnosis of analog BJT and CMOS circuits. IEEE Trans. Instr. Measur., 64, 2688‒2695.
- [18] Tadeusiewicz, M., Hałgas, S., Korzybski, M. (2002). An algorithm for soft-fault diagnosis of linear and nonlinear circuits. IEEE Trans. Cir. Syst., I. 49, 1648‒1653.
- [19] Tadeusiewicz, M., Hałgas S, Korzybski, M. (2012). Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances. Int. J. Cir. Theor. Appl., 40, 1041‒1052.
- [20] Tadeusiewicz, M., Kuczyński, A, Hałgas, S. (2015). Catastrophic fault diagnosis of a certain class of nonlinear analog circuits. Cir. Syst. Signal Process., 34, 335‒375.
- [21] Tadeusiewicz, M., Kuczyński, A., Hałgas, S. (2015). Spot defect diagnosis in analog nonlinear circuits with possible multiple operating points. Journal of Electronic Testing: Theory and Applications, 31, 491‒502.
- [22] Benson, J. (2002). Thermal characterization of packaged semiconductor devices. Technical Brief 379.3. Intersil, Milpitas, CA.
- [23] Gray, P.R., Meyer, R.G. (1993). Analysis and design of analog integrated circuits. New York: Wiley.
- [24] Kuo, F.F., Magnuson W.G. (1969). Computer oriented circuit design. Prentice-Hall.
- [25] PSpice User’s Guide. Cadence Design Systems, Inc. 2000.
- [26] www.spectrum-soft.com/faq/help/faq132.shtm, 29-08-2015.
- [27] ICAP/4-Working with model libraries. Intusoft, 2001.
- [28] HSPICE MOSFET Models Manual, Version X-2005.09. Synopsys, 2005.
Uwagi
EN
This work was supported by the Statutory Activities of Lodz University of Technology I12/1/DzS/2015.
PL
Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-2022e4ca-1764-4cfe-aa0a-0d242d6fea67