Pipelined division of signed numbers with the use of residue arithmetic in FPGA
Treść / Zawartość
An architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length of the look-up table address, a reciprocal computation algorithm based on segmentation of the divisor into two segments is used. The signed approximate reciprocal, transformed to the residue representation, is stored in look-up tables division and multiplied by the dividend in the residue form. The obtained quotient is scaled. The pipelined realization of the divider in the FPGA environment is also shown.
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