Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms

• Autorzy: Sugier J.
• Języki publikacji: EN

Abstrakty

EN

Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.

Słowa kluczowe

EN

hardware implementation; loop unrolling; pipelining; AES; BLAKE; KECCAK; SHA-3

• Wydawca: Polskie Towarzystwo Bezpieczeństwa i Niezawodności
• Czasopismo: Journal of Polish Safety and Reliability Association
• Rocznik: 2018
• Tom: Vol. 9, No. 3
• Strony: 75--84
• Opis fizyczny: Bibliogr. 14 poz., rys., tab., wykr.

Twórcy

autor

Sugier J.

• Wrocław University of Science and Technology, Faculty of Electronics, Poland

Bibliografia

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• [5] Gaj, K., Kaps J.P., Amirineni, V., Rogawski, M., Homsirikamol, E., Brewster, B.Y. (2010). ATHENa – Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. 20th International Conference on Field Programmable Logic and Applications, Milano, Italy.
• [6] Junkg, B. & Apfelbeck, J. (2011). Area-efficient FPGA implementations of the SHA-3 finalists. 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 235241.
• [7] Liberatori, M., Otero, F., Bonadero, J.C. & Castineira, J. (2007). AES-128 Cipher. High Speed, Low Cost FPGA Implementation. Proc. Third Southern Conf. on Programmable Logic. Mar del Plata, Argentina, IEEE Comp. Soc. Press.
• [8] National Institute of Standards and Technology (2001). Specification for the ADVANCED ENCRYPTION STANDARD (AES). Federal Information Processing Standards Publication 197. http://csrc.nist.gov/publications/PubsFIPS .html (accessed March 2018).
• [9] Strömbergson, J. (2008). Implementation of the Keccak hash function in FPGA devices. http://www.strombergson.com/files/Keccak_in_ FPGAs.pdf (accessed March 2018).
• [10] Sugier, J. (2014). Low cost FPGA devices in high speed implementations of KECCAK-f hash algorithm. Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds.) Proc. 9th Int. Conf. Dependability and Complex Systems DepCoS-RELCOMEX. Springer AISC, 286, 433-441.
• [11] Sugier, J. (2015). Efficiency of FPGA architectures in implementations of AES, Salsa20 and KECCAK cryptographic algorithms. J. Polish Safety and Reliability Association, 6(2), 117-124.
• [12] Sugier, J. (2016). Implementation efficiency of BLAKE and other contemporary hash algorithms in popular FPGA devices. Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds.) Dependability Engineering and Complex Systems. Proc. 11th Int. Conf. Dependability and Complex Systems DepCoSRELCOMEX. Springer AISC, 470, 457-467.
• [13] Xilinx, Inc. (2016). 7 Series FPGAs Configurable Logic Block. www.xilinx.com, ug474.pdf (accessed March 2018).
• [14] Xilinx, Inc. (2018). 7 Series FPGAs Data Sheet: Overview. www.xilinx.com, ds180.pdf (accessed March 2018.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).