Low power dynamic comparator design in 90nm technology

• Autorzy: Aneesh K. , Divya P.S. , Manoj G. , Vijila Moses

Identyfikatory

DOI

10.15199/48.2023.08.28

Warianty tytułu

PL

Konstrukcja komparatora dynamicznego małej mocy w technologii 90nm

• Języki publikacji: EN

Abstrakty

EN

This work proposes a dynamic comparator design for biomedical signal acquisition. The circuit consumes 4.598uW of power and the propagation delay is found as 39.26ps.The offset voltage variation is 1.33mV, which is the best amongst contemporary designs. The design is simulated using 90nm CMOS scale technology. The designed circuitry of the system is having only 11 number of transistors which make the system more optimised for real time application. The layout area of the design is found as 20.76um2.The circuit is simple, linear and area efficient and this makes it suitable for low power applications.

PL

W tej pracy zaproponowano projekt dynamicznego komparatora do akwizycji sygnału biomedycznego. Obwód zużywa 4,598 uW mocy, a opóźnienie propagacji wynosi 39,26 ps. Zmienność napięcia przesunięcia wynosi 1,33 mV, co jest najlepszym wynikiem wśród współczesnych projektów. Projekt jest symulowany przy użyciu technologii skali CMOS 90 nm. Zaprojektowany obwód układu ma tylko 11 tranzystorów, co sprawia, że układ jest bardziej zoptymalizowany do zastosowań w czasie rzeczywistym. Powierzchnia układu projektu wynosi 20,76 um2. Obwód jest prosty, liniowy i efektywny powierzchniowo, dzięki czemu nadaje się do zastosowań o niskim poborze mocy.

Słowa kluczowe

EN

SAR ADC; dynamic comparator; low power; dual-tail comparator design; bio-physiological signal

PL

komparator; technologia 90 nm

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2023
• Tom: R. 99, nr 8
• Strony: 161--164
• Opis fizyczny: Bibliogr. 11 poz., rys., tab.

Twórcy

autor

Aneesh K.

• Karunya Institute of Technology and Sciences, Dept. of Electronics and Communication, Coimbatore, India

• https://orcid.org/0000-0001-9279-1089

autor

Divya P.S.

• Karunya Institute of Technology and Sciences, Dept. of Mathematics, Coimbatore, India

• https://orcid.org/0000-0003-3543-5672

autor

Manoj G.

• Karunya Institute of Technology and Sciences, Dept. of Electronics and Communication, Coimbatore, India

autor

Vijila Moses

• Karunya Institute of Technology and Sciences, Dept. of Mathematics, Coimbatore, India

Bibliografia

• [1] Tang, Xiyuan, et al. "Low-power SAR ADC design: Overview and survey of state-of-the-art techniques." IEEE Transactions on Circuits and Systems I: Regular Papers (2022).
• [2] Cao, Menghua, and Weixun Tang. "The High-Speed Low-Power Dynamic Comparator." Journal of Physics: Conference Series. Vol. 2113. No. 1. IOP Publishing, 2021.
• [3] Ginés, Antonio José, et al. "Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder." International Journal of Circuit Theory and Applications 47.3 (2019): 333-349.
• [4] Bahmanyar, Parvin, et al. "Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications." Analog Integrated Circuits and Signal Processing 86 (2016): 159-169.
• [5] Van Elzakker, Michiel, et al. "A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s." IEEE Journal of Solid-State Circuits 45.5 (2010): 1007-1015.
• [6] Folla, Jérôme K., et al. "A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage." IET Circuits, Devices & Systems 15.1 (2021): 65-77.
• [7] Chevella, Subhash, Daniel O’Hare, and Ivan O’Connell. "A low-power 1-V supply dynamic comparator." IEEE Solid-State Circuits Letters 3 (2020): 154-157.
• [8] Babayan-Mashhadi, Samaneh, and Reza Lotfi. "Analysis and design of a low-voltage low-power double-tail comparator." IEEE transactions on very large scale integration (vlsi) systems 22.2 (2013): 343-352.
• [9] Savani, Vijay, and N. M. Devashrayee. "Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator." Analog Integrated Circuits and Signal Processing 93 (2017): 287-298.
• [10] Savani, Vijay, and N. M. Devashrayee. "Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator." Microelectronics journal 74 (2018): 116-126.
• [11] Varshney, Vikrant, and Rajendra Kumar Nagaria. "Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme." AEU-International Journal of Electronics and Communications 116 (2020): 153068.