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Abstrakty
A floating point accumulator cannot be obtained straightforwardly due to its pipeline architecture and feedback loop. Therefore, an essential part of the proposed floating point accumulator is a critical accumulation loop which is limited to an integer adder and 16-bit shifter only. The proposed accumulator detects a catastrophic cancellation which occurs e.g. when two similar numbers are subtracted. Additionally, modules with reduced hardware resources for rough error evaluation are proposed. The proposed architecture does not comply with the IEEE-754 floating point standard but it guarantees that a correct result, with an arbitrarily defined number of significant bits, is obtained. The proposed calculation philosophy focuses on the desired result error rather than on calculation precision as such.
Rocznik
Tom
Strony
579--587
Opis fizyczny
Bibliogr. 31 poz., rys., tab.
Twórcy
autor
- AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
autor
- AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
autor
- AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
autor
- AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
autor
- AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
- CYFRONET Academic Computer Centre, University of Science and Technology, ul. Nawojki 11, 30-950 Kraków, Poland
Bibliografia
- [1] Xilinx Inc., “Floating point Operator v5.0”, DS335 June 24, 2009, www.xilinx.com.
- [2] Altera Ltd. “Floating-Point IP Cores User Guide”, UG-01058, 2016.12.09, www.altera.com.
- [3] A. Gramacki, M. Sawerwain, and J. Gramacki, “FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach”, Bull. Pol. Ac.: Tech 64(4), 821–829 (2016).
- [4] E. Jamro, T. Pabiś, P. Russek, and K. Wiatr, “The algorithms for FPGA implementation of sparse matrices multiplication”, Computing and Informatics 33(3), 667–684 (2014).
- [5] M. Karwatowski, P. Russek, M. Wielgosz, S. Koryciak, and K. Wiatr, “Energy efficient calculations of text similarity measure on FPGA-accelerated computing platforms”, Parallel Processing and Applied Mathematics, PPAM, Lecture Notes in Computer Science, Springer, Cham 9573, 31–40 (2015).
- [6] E. Jamro, P. Russek, A. Dabrowska-Boruch, and et al., “The implementation of the customized, parallel architecture for a fast word-match program”, Computer Systems Science And Engineering 26, 285‒292 (2011).
- [7] M. Wielgosz and M. Pietron, “Using spatial pooler of hierarchical temporal memory to classify noisy videos with predefined complexity”, Neurocomputing 240, 84–97 (2017).
- [8] A. Głowacz and Z. Głowacz, “Recognition of rotor damages in a DC motor using acoustic signals”, Bull. Pol. Ac.: Tech 65(2), 187–194 (2017).
- [9] A.R. Lopes and G.A. Constantinides, “A fused hybrid floating point dot-product for FPGAs”, ARC’2010 Bangkok, Thailand, LNCS 5992, March 2010, 157‒168.
- [10] M. de Lorimier and A. De Hon, “Floating point sparse matrix-vector multiply for FPGAs”, Proceedings of the International Symposium on Field-Programmable Gate Arrays, 75‒78 (2005).
- [11] L. Zhuo, G.R. Morris, and V.K. Prasanna, “Designing scalable FPGA-based reduction circuits using pipelined floating point cores”, Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS’05 (2005).
- [12] X. Wang, S. Braganza, and M. Leeser, “Advanced components in the variable precision floating point library”, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (2006).
- [13] F. de Dinechin, B. Pasca, O. Cret, and R. Tudoran, “An FPGAspecific approach to floating point accumulation and sumofproducts”, ICECE Technology, FPT 2008 10 Dec, 33‒40 (2008).
- [14] U. Kulisch, “Very fast and exact accumulation of products”, ISC 2010, Hamburg, (2010).
- [15] Y. Uguen and F. de Dinechin, “Designs pace exploration for the Kulisch accumulator”, 2017. .
- [16] IFIP WG, “IEEE P1788 letter”, dated Sep. 9 2009.
- [17] Z. Luo and M. Martonosi, “Accelerating pipelined integer and floating point accumulations in configurable hardware with delayed addition techniques”, IEEE Transactions On Computers 49 (3), 208‒218 (2000).
- [18] S.R. Vangal, Y.V. Hoskote, N.Y. Borkar, and A. Alvandpour, ”A 6.2-GFlops Floating point Multiply-Accumulator with Conditional Normalization”, IEEE Journal of Solid-State Circuits 41 (10), 2314‒2323 (2006).
- [19] A. Paidimarri, A. Cevrero, P. Brisk, and P. Ienne, “FPGA implementation of a single-precision floating point multiply-accumulator with single-cycle accumulation”, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, 267‒270 (2009).
- [20] S. Jain, V. Erraguntla, S.R. Vangal, Y. Hoskote, N. Borkar, T. Mandepudi, and Karthik VP, “A 90mW/GFlop 3.4GHz reconfigurable fused/continuous multiply-accumulator for floating point and integer operands in 65nm”, VLSID, 23rd International Conference on VLSI Design, 2010, pp. 252‒257.
- [21] T.O. Bachir and J.-P. David, “Performing floating point accumulation on a modern FPGA in single and double precision”, 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 105‒108 (2010).
- [22] K.K. Nagar and J.D. Bakos, “A High-Performance Double Precision Accumulator”, Proc. IEEE International Conference on Field-Programmable Technology (IC-FPT’09), Dec. 9‒11, 2009, 500‒503.
- [23] J. Liang, R. Tessier, and O. Mencer, “Floating Point Unit Generation and Evaluation for FPGAs”, Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’03), 185‒194.
- [24] M. Daumas and D.W. Matula, “Validated Roundings of Dot Products by Sticky Accumulation”, IEEE Transactions on Computers 46(5), 623‒629 (1997).
- [25] N. Kapre and A. DeHon, “Optimistic parallelization of floating point accumulation”, 18th IEEE Symposium on Computer Arithmetic. Proceedings/Symposium on Computer Arithmetic. IEEE, Los Alamitos, CA, 2007, 205‒216.
- [26] J. Demmel and H.D. Nguyen, “Parallel reproducible summation”, IEEE Trans. on Computers 64(7), 2060‒2070 (2015).
- [27] Xilinx Inc., “Performance and resource utilization for floatingpoint, v7.1”, https://www.xilinx.com/support/documentation/ip_documentation/ru/floating-point.html.
- [28] E. Jamro, K. Wiatr, and M. Wielgosz, “FPGA implementation of 64-bit exponential function for HPC”, 2007 International conference on Field programmable logic and applications (FPL), Amsterdam, Netherlands, August 27–29, 2007, 718–721.
- [29] J.M. Muller, Elementary Functions, Algorithms and Implementation, Brikhauser, Boston, 2005.
- [30] M.O. Lam, J.K. Hollingsworth, and G.W. Stewart, “Dynamic Floating point Cancellation Detection”, Parallel Computing 39(3), 146–155 (2013).
- [31] J.R. Shewchuk, “Robust adaptive floating point geometric predicates”, Proc. 12th Annu. ACM Sympos. Comput. Geom., 141−150 (1996).
Uwagi
PL
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-1e5c5c6d-5f21-4fb3-8212-1375832118f7