Novel architecture for floating point accumulator with cancelation error detection

• Autorzy: Jamro E. , Dąbrowska-Boruch A. , Russek P. , Wielgosz M. , Wiatr K.

Identyfikatory

DOI

10.24425/bpas.2018.124273

• Języki publikacji: EN

Abstrakty

EN

A floating point accumulator cannot be obtained straightforwardly due to its pipeline architecture and feedback loop. Therefore, an essential part of the proposed floating point accumulator is a critical accumulation loop which is limited to an integer adder and 16-bit shifter only. The proposed accumulator detects a catastrophic cancellation which occurs e.g. when two similar numbers are subtracted. Additionally, modules with reduced hardware resources for rough error evaluation are proposed. The proposed architecture does not comply with the IEEE-754 floating point standard but it guarantees that a correct result, with an arbitrarily defined number of significant bits, is obtained. The proposed calculation philosophy focuses on the desired result error rather than on calculation precision as such.

Słowa kluczowe

EN

floating point arithmetic; computing error; approximate computing

PL

arytmetyka zmiennoprzecinkowa; błąd obliczeniowy; obliczenia przybliżone

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2018
• Tom: Vol. 66, nr 5
• Strony: 579--587
• Opis fizyczny: Bibliogr. 31 poz., rys., tab.

Twórcy

autor

Jamro E.

• AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland

autor

Dąbrowska-Boruch A.

• AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland

autor

Russek P.

• AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland

autor

Wielgosz M.

• AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland

autor

Wiatr K.

• AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Kraków, Poland
• CYFRONET Academic Computer Centre, University of Science and Technology, ul. Nawojki 11, 30-950 Kraków, Poland

Bibliografia

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Uwagi

PL

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).