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Modified Dual Second-order Generalized Integrator FLL for Frequency Estimation Under Various Grid Abnormalities

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Proper synchronization of Distributed Generator with grid and its performance in grid-connected mode relies on fast and precise estimation of phase and amplitude of the fundamental component of grid voltage. However, the accuracy with which the frequency is estimated is dependent on the type of grid voltage abnormalities and structure of the phase-locked loop or frequency locked loop control schemes. Among various control schemes, second-order generalized integrator based frequency- locked loop (SOGI-FLL) is reported to have the most promising performance. It tracks the frequency of grid voltage accurately even when grid voltage is characterized by sag, swell, harmonics, imbalance, frequency variations etc. However, estimated frequency contains low frequency oscillations in case when sensed grid-voltage has a dc offset. This paper presents a modified dual second-order generalized integrator frequency-locked loop (MDSOGI-FLL) for three-phase systems to cope with the non-ideal three-phase grid voltages having all type of abnormalities including the dc offset. The complexity in control scheme is almost the same as the standard dual SOGI-FLL, but the performance is enhanced. Simulation results show that the proposed MDSOGI-FLL is effective under all abnormal grid voltage conditions. The results are validated experimentally to justify the superior performance of MDSOGI-FLL under adverse conditions.
Rocznik
Strony
10--18
Opis fizyczny
Bibliogr. 25 poz., rys., tab.
Twórcy
autor
  • Department of Electrical Engineering Sarvajanik College of Engineering & Technology, Surat, India
autor
  • Department of Electrical Engineering, Sarvajanik College of Engineering & Technology, Surat, India
Bibliografia
  • [1] F. Blaabjerg, Zhe Chen, and S. Baekhoej Kjaer, “Power electronics as efficient interface in dispersed power generation systems, ” IEEE Trans. on Power Electron., vol. 19, no. 5, pp. 1184-1194, September 2004.
  • [2] F. Blaabjerg, Remus Teodorescu, Marco Liserre, and Adrian V. Timbus, “ Overview of control and grid synchronization for distributed power generation systems”, IEEE Trans. on Ind. Electron., vol. 53, no. 5, pp. 1398-1409, October 2006.
  • [3] Se-Kyo Chung, “A phase tracking system for three phase utility interface inverters,” IEEE Trans. Power Electron. , vol. 15, no. 3, pp. 431-438, May 2000.
  • [4] Benjamin Kroposki, Christopher Pink, Richard DeBlasio, Marcelo Simoes, Holly Thomas and Pankaj K. Sen “Benefits of power electronic interfaces for distributed energy systems,” IEEE Trans. on Energy Conv., vol. 25, no. 3, pp. September 2010.
  • [5] Maohai Wang and Yuanzhang Sun, “A practical method to improve phasor and power measurement accuracy of DFT algorithm,” in IEEE Trans. on Power Del., vol. 21, no. 3, pp. 1054-1062, July 2006.
  • [6] H. A. Darwish and M. Fikri, “Practical considerations for recursive DFT implementation in numerical relays,” in IEEE Trans. on Power Del., vol. 22, no. 1, pp. 42-49, Jan 2007.
  • [7] H. Wen, Z. Teng, Y. Wang and X. Hu, "Spectral correction approach based on desirable sidelobe window for harmonic analysis of industrial power system," in IEEE Trans. on Ind. Electron., vol. 60, no. 3, pp. 1001-1010, March 2013.
  • [8] R. Teodorescu, M. Liserre and P. Rodriguez, “A thesis on grid converters for photovoltaic and wind power systems,” 2011, ISBN: 978-0-470-05751-3.
  • [9] Md. Shamim Reza, Mihai Ciobotaru and V. G. Agelidis, “Accurate estimation of single-phase grid voltage parameters under distorted conditions,” IEEE Trans. Power Del. vol. 29, no. 3, pp. 1138-1146, June-2014.
  • [10] Fengjiang Wu, Lujie Zhang, and Jiandong Duan, “A new two-phase stationary-frame-based enhanced PLL for three-phase grid synchronization,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 62, no. 3, March 2015.
  • [11] Y. Han, M. Luo, X. Zhao, J. M. Guerrero and L. Xu, "Comparative performance evaluation of orthogonal-signal-generators-based single-phase PLL algorithms-A survey," in IEEE Trans. on Power Electron., vol. 31, no. 5, pp. 3932-3944, May 2016.
  • [12] V. Kaura and V. Blasco, “Operation of a phase locked loop system under distorted utility conditions,” IEEE Trans. Ind. Appl., vol. 33, no.1, pp. 58-63, Jan 1997.
  • [13] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos and D. Boroyevich, “Decoupled double synchronous reference frame PLL for power converters control,” in IEEE Trans. on Power Electron., vol. 22, no. 3, pp. 1078-1078, May 2007.
  • [14] P. Rodriguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, “Grid synchronization of power converters using multiple second-order generalized integrators,” in Proc. 34a'Annu. Conf. IEEE Ind. Electron., pp. 755-760, November 2008.
  • [15] P. Rodriguez, A. Luna, R. Santiago M. Aguilar, I. E. Otadui, R. Teodorescu, and F. Blaabjerg, “A stationary reference frame grid synchronization system for three-phase grid-connected power converters under adverse grid conditions,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 99-112, January 2012.
  • [16] Saeed Golestan, Malek Ramezani, Josep. M. Guerrer, and Mohammad Monfared, “dq-Frame Cascaded Delayed Signal Cancellation- Based PLL: Analysis, Design, and Comparison With Moving Average Filter-Based PLL,” IEEE Trans. Power Electron., vol. 30, no. 3, pp. 1618-1631, March 2015.
  • [17] Md. Shamim Reza, Mihai Ciobotaru, and V. G. Agelidis, “Power system frequency estimation by using a Newton-type technique for smart meters,” IEEE Trans. Instrum. Meas., vol. 64, no. 3, pp. 615-624, March -2015.
  • [18] J. Matas, M. Castilla, J. Miret, L. Garcia de Vicuna, and R. Guzman, “An adaptive prefiltering method to improve the speed/accuracy tradeoff of voltage sequence detection methods under adverse grid conditions,” IEEE Trans. on Ind. Electron., vol. 61, no. 5, pp. 2139-2151, May-2014.
  • [19] M. Ciobotaru, R. Teodorescu and V. G. Agelidis, “Offset rejection for PLL based synchronization in grid-connected converters,” Proc. 23rd Annu. IEEE Appl. Power Energy Conf. Expo., pp. 1611-1617, February-2008.
  • [20] M. Karimi Ghartemani, S. Khajehoddin, P. Jain, and A. Bakhshai. “Comparison of two methods for addressing dc component in phase-locked loop (PLL) systems,” in Proc. IEEE ECCE, pp. 3053-3058, September 2011.
  • [21] M. Karimi-Ghartemani, S. Khajehoddin, P. Jain, A. Bakhshai and M. Mojiri, “Addressing dc component in PLL and notch filter algorithms,” IEEE Trans. Power Electron. , vol. 27, no. 1, pp. 78-86, January 2012.
  • [22] S. Hwang, L. Liu, H. Li, and J. M. Kim, “DC offset error compensation for synchronous reference frame PLL in single-phase grid-connected converters,” IEEE Trans. Power Electron. , vol. 27, no. 8, pp. 3467-3471, August 2012.
  • [23] Fengjiang Wu, Dongyang Sun, Lujie Zhang and Jiandong Duan, “Influence of plugging DC offset estimation integrator in single-phase EPLL and alternative scheme to eliminate effect of input DC offset and harmonics,” IEEE Trans. on Ind. Electron., vol. 62, no. 8, pp. 4823-4831, May-2014.
  • [24] S. Golestan, Josep M. Guerrero and G.B. Gharehpetian, “Five approaches to deal with problem of DC offset in phase-locked loop algorithm: Design consideration and performance evaluation,” IEEE Trans. Power Electron. , vol. 31, no. 1, pp. 648-661, January 2016.
  • [25] K. R. Patil and Hiren H. Patel, “Modified dual second-order generalised integrator FLL for synchronization of a distributed generator to a weak grid,” in Proc. 16hAnnu. Conf. IEEE-EEEIC, June 2016.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-1d7adaf3-2b2a-4b32-8366-bd0425cbd0f2
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