High level synthesis in FPGA of TCS/RNS converter

• Autorzy: Smyk R. , Czyżak M.

Identyfikatory

DOI

10.21008/j.1897-0737.2017.91.0014

• Konferencja: Computer Applications in Electrical Engineering (10-11.04.2017 ; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.

Słowa kluczowe

EN

high–level synthesis; residue number system; FPGA; C++ language; two's complement–to–residue converter

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2017
• Tom: No. 91
• Strony: 143--154
• Opis fizyczny: Bibliogr. 8 poz., rys.

Twórcy

autor

Smyk R.

• Gdansk University of Technology

autor

Czyżak M.

• Gdansk University of Technology

Bibliografia

• [1] Meeus W., Van Beeck K., Goedemé T., Meel J., Stroobandt D., An overview of today’s high–level synthesis tools, DOI 10.1007/s10617–012–9096–8, Springer, 2012.
• [2] Szabo N.S. and Tanaka R.J., Residue Arithmetic and its Applications to Computer Technology, New York, McGraw–Hill, 1967.
• [3] Soderstrand M. et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, NY, 1986.
• [4] Alia G., Martinelli E., "VLSI binary–residue converters for pipelined processing", Computer J., vol. 33, no.5, pp. 473–475, 1990.
• [5] Piestrak S.J., Design of residue generators and multioperand modulo adders using carry–save adders, IEEE Trans. Comp., Volume 43, Pages 68–77, Jan. 1994.
• [6] Premkumar A.B., A formal framework for conversion from binary to residue numbers, IEEE Trans. Circuits and Systems–II, Volume 49, Number 2, Pages 135–144, Feb.2002.
• [7] Czyżak M., High–speed binary–to–residue converter with improved architecture, 27th Int. Conf. on Fundamentals of Electrotechnics and Circuit Theory, Gliwice–Niedzica, May 26–29, Pages 431–436, 2004.
• [8] Premkumar A.B., Improved memoryless RNS forward converter based on periodicity of residues, IEEE Trans. Circuits and Systems–II, Express Briefs, Volume 53, Number 2, Pages 133–137, Feb. 2006.

Uwagi

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).