Downscaling and short channel effects in twin gate junctionless vertical slit FETs

• Autorzy: Barbut L , Jazaeri F , Bouvet D , Sallese J.-M.
• Języki publikacji: EN

Abstrakty

EN

In this work, we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs.

Słowa kluczowe

EN

junctionless; VeSFET; DIBL; SCE; design space

PL

VeSFET; DIBL; SCE; przestrzeń projektowa

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 3
• Strony: 103--109
• Opis fizyczny: Bibliogr. 14 poz.

Twórcy

autor

Barbut L

• Institute of Electrical Engineering, Ecole Polytechnique Féderale de Lausanne, 1015 Lausanne, Switzerland

autor

Jazaeri F

• Institute of Electrical Engineering, Ecole Polytechnique Féderale de Lausanne, 1015 Lausanne, Switzerland

autor

Bouvet D

• Center of Micro and Nano Technology (CMi), Ecole Polytechnique Fedérale de Lausanne, 1015 Lausanne, Switzerland

autor

Sallese J.-M.

• Institute of Electrical Engineering, Ecole Polytechnique Féderale de Lausanne, 1015 Lausanne, Switzerland

Bibliografia

• [1] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions”, Nat. Nanotechnol., vol. 15, pp. 1-5, Feb. 2010.
• [2] J.-P. Colinge, A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, and P. Razavi, “Junctionless Nanowire Transistor (JNT): Properties and design guidelines,” Solid. State. Electron., vol. 65-66, pp. 33-37, Nov. 2011.
• [3] S. Migita, Y. Morita, M. Masahara, and H. Ota, “Electrical performances ofjunctionless-FETs at the scaling limit (Lch = 3 nm),” in International Electron Devices Meeting, vol. 8, no. 6, pp. 1-4, 2012.
• [4] A. Koukab, F. Jazaeri, and J.-M. Sallese, “On performance scaling and speed of junctionless transistors,” Solid. State. Electron., vol. 79, pp. 18-21, Aug. 2013.
• [5] W. Maly, “Integrated Circuit Device, System, and Method of Fabrication,” 0321830/2009.
• [6] W. Maly, N. Singh, Z. Chen, N. Shen, X. Li, A. Pfitzner, D. Kasprowicz, W. Kuzmicz, Y.-W. Lin, and M. Marek-Sadowska, “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 145-150, 2011.
• [7] Z. Chen, A. Kamath, N. Singh, N. Shen, and X. Li, “N-channel Junction-less Vertical Slit Field-Effect Transistor (VeSFET): Fabrication-based Feasibility Assessment,” in International Proceedings of Computer Science and Information Technology, vol. 32, 2012.
• [8] X. Qiu, M. Marek-Sadowska, and W. Maly, “Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure,” Proc. 2013 ACM Int. Symp. Int. Symp. Phys. Des. - ISPD ’l3, p. 130-136, 2013.
• [9] A. Kamath, Z. Chen, N. Shen, N. Singh, G. Lo, D.-L. Kwong, D. Kasprowicz, A. Pfitzner, and W. Maly, “Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor,” Electron Device Lett. IEEE, vol. 33, no. 2, pp. 152-154, Feb. 2012.
• [10] V. S. Nandakumar and M. Marek-Sadowska, “A Low Energy Network- on-Chip Fabric for 3-D Multi-Core Architectures,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 2, no. 2, pp. 266-277, Jun. 2012.
• [11] M. Pastre, F. Krummenacher, L. Barbut, J.-M. Sallese, and M. Kayal, “Towards Circuit Design Using VeSFET,” in Mixed Design of Integrated Circuits and Systems (MIXDES), no. 200021, pp. 139-144, 2011.
• [12] X. Qiu, M. Marek-Sadowska, and W. Maly, “Vertical Slit Field Effect Transistor in Ultra-Low Power Applications,” in Quality Electronic Design (ISQED), pp 384-390, 2012.
• [13] F. Jazaeri, L. Barbut, and J.-M. Sallese, “Modeling and Design Space of Junctionless Symmetric DG MOSFETs with Long Channel,” Electron Devices, IEEE Trans., vol. 60, no. 7, pp. 2120-2127, 2013.
• [14] L. Barbut and F. Jazaeri, “Transient Off-Current in Junctionless FETs,” Electron Devices, IEEE Trans., vol. 60, no. 6, pp. 2080-2083, 2013.