New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

• Autorzy: Tadeusiewicz M. , Hałgas S. , Kuczyński A.

Identyfikatory

DOI

10.1515/eletel-2015-0011

• Języki publikacji: EN

Abstrakty

EN

The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits having multiple DC operating points. To solve these problems several methods have been recently developed, which employ different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated. All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits. To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke’s algorithm are employed. For illustration four numerical examples are given.

Słowa kluczowe

EN

analog circuits; fault diagnosis; local and global diagnosis; multiple soft fault; nonlinear circuits; single hard faults

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2015
• Tom: Vol. 61, No. 1
• Strony: 83--93
• Opis fizyczny: Bibliogr. 38 poz., rys., wykr.

Twórcy

autor

Tadeusiewicz M.

• Department of Electrical, Electronic, Computer and Control Engineering, Łódź University of Technology, Stefanowskiego 18/22, 90-924 Łódź, Poland

autor

Hałgas S.

• Department of Electrical, Electronic, Computer and Control Engineering, Łódź University of Technology, Stefanowskiego 18/22, 90-924 Łódź, Poland

autor

Kuczyński A.

• Department of Electrical, Electronic, Computer and Control Engineering, Łódź University of Technology, Stefanowskiego 18/22, 90-924 Łódź, Poland

Bibliografia

• [1] Aminian M., Aminian F., ”A modular fault-diagnosis system for analog electronic circuits using neural networks with wavelet transform as apreprocesor”, IEEE Trans. Instrum. Meas., Vol. 56, 1546-1554, DOI: 10.1109/TIM.2007.904549, 2007.
• [2] Bilski P., Wojciechowski J., ”Rough-sets-based reduction for analog systems diagnostics”, IEEE Trans. Instrum. Measur., Vol. 60, 880-890, DOI 10.1109/TIM.2010.2060225, 2011.
• [3] Bing Long, Min Li, Houjun Wang, Shulin Tian, ”Diagnostics of analog circuits based on LS-SVM using time domain features”, Circuits Syst. Signal Process., Vol. 32, 2683-2706, DOI 10.1007/s00034-013-9614-3, 2013.
• [4] Catelani M., Fort A., ”Soft fault detection and isolation in analog circuits: some results and a comparison between a fuzzy approach and radial basis function networks”, IEEE Trans. Instrum. Measur, Vol. 51, 196-202, DOI 10.1109/19.997811, 2002.
• [5] Cherubal S., Chatterjee A., ”Test generation based diagnosis of device parameters for analog circuits”, Proceedings of the Design, Automation and Test in Europe, 596-602, DOI 10.1109/DATE.2001.915084, 2001.
• [6] Cottle R.W., Pang J.S., Stone R.E., The Linear Complemen tarity Problem, Academic Press, New York, 1992.
• [7] Czaja Z., ”Self-testing of analog parts terminated by ADCs based on multiple sampling of time response”, IEEE Trans. Instr. Measur., Vol. 62, 3160-3167, DOI 10.1109/TIM.2013.2272867, 2013.
• [8] Fedi G., Giomi R., Luchetta A., Manetti S., Piccirilli M. C., ”On the application of symbolic techniques to the multiple fault location in low testability analog circuits”, IEEE Trans. Cir. Syst. II., Vol. 45, 1383-1388, DOI 10.1109/82.728851, 1998.
• [9] Garcia C.B., Zangwill W.I., Pathways to Solutions, Fixed Points, and Equilibria, Series in Computational Mathematics, Prentice-Hall, New York, 1981.
• [10] Gizopoulos D., Advances in Electronic Testing. Challenges and Methodologies, Springer, Dordrecht, 2006.
• [11] Golonek T., Rutkowski J., ”Genetic-algorithm-based method for optimal analog test points selection”, IEEE Trans. Cir. Syst. II, Vol. 54, 117-121, DOI 10.1109/TCSII.2006.884112, 2007.
• [12] Grasso F., Manetti S., Piccirilli M. C., ”An approach to analog fault diagnosis using genetic algorithms”, Proc. IEE Conf., MELECON 2004, Vol. 1, 111-114, DOI 10.1109/MELCON.2004.1346785, 2004.
• [13] Jantos P., Grzechca D., Rutkowski J., ”A global parametric fault diagnosis with the use of artificial neural networks”, Proceedings of the European Conference on Circuit Theory and Design, 651-654, DOI 10.1109/ECCTD.2009.5275063, 2009.
• [14] Jantos P., Grzechca D., Rutkowski J., ”Global parametric faults identification with the use of Diferential Evolution”, Proceedigs of the 12th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 222-225, DOI 10.1109/DDECS.2009.5012133, 2009.
• [15] Kabisatpathy P., Barua A., Sinha S., Fault Diagnosis of Analog Integrated Circuits, Springer, Dordrecht, 2005.
• [16] Liu D., Starzyk J.A., ”A generalized fault diagnosis in dynamic analog circuits”, Int. J. Cir. Theor. Appl., Vol. 30, 487-510, DOI 10.1002/cta.187, 2002.
• [17] Materka A., Strzelecki M., ”Parametric testing of mixed-signal circuits by ANN processing of transient responses”, Journal Electron. Test.: Theory and Appl., Vol. 9, 187-202, DOI 10.1007/BF00137574, 1996.
• [18] Osowski S., Sałat R., ”Support vector machine for soft fault location in electrical circuits”, Journal of Intelig. Fuzzy Syst., Vol. 22, 21-31, DOI 10.3233/IFS-2010-0471, 2011.
• [19] Papakostas D.K., Hatzopoulos A.A., ”A unified procedure for fault detection of analog and mixed-mode circuits using magnitude and phase components of the power supply current spectrum”, IEEE Trans. Instrum. Measur., Vol. 57, 2589-2995, DOI 10.1109/TIM.2008.924932, 2008.
• [20] Richter S.L., DiCarlo R.A., ”Continuation methods: theory and applications”, IEEE Trans. Cir. Syst., Vol. 30, 347-352, DOI 10.1109/TCS.1983.1085373, 1983.
• [21] Robotycki A., Zielonko R., ”Fault diagnosis of analog piecewise linear circuits based on homotopy”, IEEE Trans. Instrum. Measur., Vol. 51, 876- 881, DOI 10.1109/TIM.2002.803515, 2002.
• [22] Rutkowski J., Słownikowe metody diagnostyczne analogowych układów elektronicznych, WKŁ, Warszawa, 2003.
• [23] Spyronasios A.D., Dimopoulos M.G., Hatzopoulos A.A., ”Wavelet analysis for the detection of parametric and catastrophic faults in mixed-signal circuits”, IEEE Trans. Instr. Measur., Vol. 60, 2025-2038, DOI 10.1109/TIM.2011.2115550, 2011.
• [24] Starzyk J.A., Liu D., Liu Z.H., Nelson D.E., Rutkowski J.O., ”Entropy-based optimum test points selection for analog fault dictionary techniques”, IEEE Trans. Inst. Measur., Vol. 53, 754-761, DOI 10.1109/TIM.2004.827085, 2004.
• [25] Tadeusiewicz M., Korzybski M., ”A method for fault diagnosis in linear electronic circuits”, Int. J. Cir. Theor. Appl., Vol. 28, 245-262, DOI 10.1002/(SICI)1097-007X(200005/06)28:3<245::AID-CTA103>3.0.CO;2-X, 2000.
• [26] Tadeusiewicz M., Hałgas S., Korzybski M., ”An algorithm for soft-fault diagnosis of linear and nonlinear circuits”, IEEE Trans. Cir. Syst. - I, Vol. 49, 1648-1653, DOI 10.1109/TCSI.2002.804596, 2002.
• [27] Tadeusiewicz M., Hałgas S., ”An algorithm for multiple fault diagnosis in analogue circuits”, Int. J. Cir. Theor. Appl., Vol. 34, 607-615, DOI 10.1002/cta.374, 2006.
• [28] Tadeusiewicz M., Hałgas S., ”A method for fast simulation of multiple catastrophic faults in analogue circuits”, Int. J. Circ. Theor. Appl., Vol. 38, 275-290, DOI 10.1002/cta.570, 2010.
• [29] Tadeusiewicz M., Hałgas S., ”Multiple soft fault diagnosis of nonlinear circuits using the continuation method”, Journal of Electronic Testing: Theory and Applications, Vol. 28, 487-493, DOI 10.1007/s10836-012-5306-3, 2012.
• [30] Tadeusiewicz M., Hałgas S., Korzybski M., ”Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances”, Int. J. Circ. Theor. Appl., Vol. 40, 1041-1052, DOI 10.1002/cta.770, 2012.
• [31] Tadeusiewicz M., Hałgas S., ”Global and local parametric diagnosis of analog short-channel CMOS circuits using homotopy-s implicial algorithm”, Int. J. Cir. Theor. Appl., Vol. 42, 1051-1068, DOI 10.1002/cta.1904, 2014.
• [32] Tadeusiewicz M., Hałgas S., ”Multiple soft fault diagnosis of analog circuits using restart homotopy method ”, Elektronika, Vol. 12, 87-91, 2013.
• [33] Tadeusiewicz M., Kuczy ́nski A., ”A very fast method for the DC analysis of diode-transistor circuits”, Circuits Syst. Signal Process., Vol. 32, 433-451, DOI 10.1007/s00034-012-9469-z, 2013.
• [34] Tadeusiewicz M., ”Nowe koncepcje diagnostyki nieliniowych układów analogowych”, Mat. Międzynarodowej Konf. z Podstaw Elektrotechn. i Teorii Obwodów, 3-3j, 2014.
• [35] Tadeusiewicz M., Hałgas S., ”Multiple soft fault diagnosis of BJT circuits”, Metr. Measur. Syst., Vol. 21, 663-674, 2014.
• [36] Tadeusiewicz M., Kuczy ́nski A., Hałgas. S., ”Catastrophic fault diagnosis of a certain class of nonlinear analog circuits”, Circuits Syst. Signal Process., Vol. 34, 353-375, DOI 10.1007/s00034-014-9857-7, 2015.
• [37] Toczek W., Kowalewski M., ”Built-in test scheme for detection, classification and evaluation of nonlinearities”, Metr. Measur. Syst., Vol. 16, 47-61, 2009.
• [38] Zielonko R., Królikowski A., Metody pomiarowo-diagnostyczne analogowych układów elektronicznych, WNT Warszawa, 1988.