A Single-chip Integration Approach of Switching Cells Suitable for Medium Power Applications

• Autorzy: El-Khadiry A , Bourennane A , Richardeau F , Imbernon E , Breil M
• Języki publikacji: EN

Abstrakty

EN

This paper deals with the monolithic integration of switching cells that are used in power electronics for the realization of static power converters. The aim of the monolithic integration of the power switching cells is to suppress wire bonds in order to improve electrical performance as well as reliability of power modules intended for medium power applications. Within this context, the single chip integration approach presented in this paper constitutes a solution and a promising approach that combines judiciously multiple reverse conducting IGBT switches in a single Si-chip. The operating modes of the integrated structure are validated in an inverter application using 2D Sentaurus simulations. The targeted packaging of the single chip converter on DBC/IMS substrates doesn’t use any wire bonding and doesn’t exhibit any dv/dt stress directly on the DBC/IMS substrates.

Słowa kluczowe

EN

monolithic integration; on-chip integration; power conversion; switching cells; inverter

PL

integracja monolityczna; integracja on-chip; przetwarzanie mocy; inwertor

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 2
• Strony: 43--48
• Opis fizyczny: Bibliogr. 7 poz.

Twórcy

autor

El-Khadiry A

• CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France
• CNRS, LAPLACE, 2 rue Charles Camichel, F-31071 Toulouse, France
• Université de Toulouse, UPS, F-31400 Toulouse, France

autor

Bourennane A

• CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France
• Université de Toulouse, UPS, F-31400 Toulouse, France

autor

Richardeau F

• CNRS, LAPLACE, 2 rue Charles Camichel, F-31071 Toulouse, France
• Université de Toulouse; INP, UPS; LAPLACE (Laboratoire Plasma et conversion d’ Energie) ENSEEIHT, 2 rue Charles Camichel, BP 7122, F-31071 Toulouse, France

autor

Imbernon E

• CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France

autor

Breil M

• CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France
• Université de Toulouse, UPS, F-31400 Toulouse, France

Bibliografia

• [1] Green, D. W, Shankar Narayanan, E. M, „Fully Isolated High Side and Low Side LIGBTs in Junction Isolation Technology” Power Semiconductor Devices and IC’s, 2006. ISPSD 2006. IEEE International Symposium on Poser Semicondutor Devices , pp.1-4, 4-8 June 2006.
• [2] A. Bourennane, M. Breil-Dupuy, F. Richardeau and J-L. Sanchez. Patent number : 11/59137, Date : Oct. 10 - 2011, by : Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique de Toulouse. Title: „Cellule monolithique de circuit intégré et notamment cellule de commutation monolithique”.
• [3] A. El-Khadiry, A. Bourennane , M. Breil and F. Richardeau “Monolithically integrated switching cells suitable for high density power conversion” (ISPS’12), Prague, pp. 222-227, 29 - 31 August 2012.
• [4] L. Storasta, et al. “A comparison of charge dynamics in the reverse- conducting RC IGBT and Bi-mode Insulated Gate Transistor BiGT” (ISPSD’10), pp.391, 6-10 June 2010.
• [5] L. Benaissa et al. “A vertical power device conductive assembly at wafer level using direct bonding technology” (ISPSD’12), Bruges, p. 77-80, 3-7 June 2012.
• [6] J.-L. Sanchez, E. Scheid, P. Austin, M. Breil, H. Carrière, P. Dubreuil, E. Imbernon, F. Rossel, B. Rous set “Realization of vertical P+ walls through wafer for bi-directional current and voltage power integrated devices” IEEE, ISPSD’03, pp. 195-198, Cambridge. England.
• [7] Synopsis, Inc., TCAD Sentaurus, version G-2012.06.