100 Gbps wireless – data link layer VHDL implementation

• Autorzy: Lopacinski L. , Nolte J. , Buechner S. , Brzozowski M. , Kraemer R.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we describe implementation and hardware used for a wireless 100 Gbps data link layer demonstrator. So fast stream processing requires a highly parallelized approach. The timing requirements of the 100 Gbps networks are so demanding that there is no chance to deal with this task as a single stream in a field programmable gate array (FPGA). Due to this reason, we introduce and validate one of possible architectures that can solve the task. The 100 Gbps implementation is explained in detail, and the most important parameters of the FPGA design are mentioned.

Słowa kluczowe

EN

data link layer; wireless; 100 Gbps; FPGA

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2015
• Tom: Vol. 61, No. 7
• Strony: 333--336
• Opis fizyczny: Bibliogr. 18 poz., rys., schem., tab., wykr.

Twórcy

autor

Lopacinski L.

• Brandenburg University of Technology, Cottbus, Germany

autor

Nolte J.

• Brandenburg University of Technology, Cottbus, Germany

autor

Buechner S.

• Brandenburg University of Technology, Cottbus, Germany

autor

Brzozowski M.

• IHP, Frankfurt Oder, Germany

autor

Kraemer R.

• IHP, Frankfurt Oder, Germany

Bibliografia

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