Exact parallel critical path fault tracing to speed-up fault simulation in sequential circuits

• Autorzy: Kõusaar Jaak , Kostin Sergei , Ubar Raimund , Devadze Sergei , Raik Jaan
• Języki publikacji: EN

Abstrakty

EN

We propose a new method to speed up stuck-at fault simulation for sequential circuits. The method combines exact parallel critical path tracing of faults, used so far only for combinational circuits, with traditional fault simulation in sequential circuits. For that purpose, formulas are developed for classification of faults into two classes: the faults eligible for parallel critical path tracing, and the faults which have to be simulated over the global feedbacks in the circuit by traditional methods. Combining these two approaches in fault simulation ‒ the combinational and sequential simulation concepts ‒ allows dramatic speed-up of fault simulation in sequential circuits, which is demonstrated by experimental results.

Słowa kluczowe

EN

sequential circuits; fault simulation; stuck-at-faults; critical path tracing

PL

układy sekwencyjne; symulacja błędów

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2018
• Tom: Vol. 9, nr 1
• Strony: 9--18
• Opis fizyczny: Bibliogr. 18 poz.

Twórcy

autor

Kõusaar Jaak

• Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia

autor

Kostin Sergei

• Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia

autor

Ubar Raimund

• Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia

autor

Devadze Sergei

• Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia

autor

Raik Jaan

• Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia

Bibliografia

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Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).