Implementation of fast uniform random number generator on FPGA

• Autorzy: Kozierski P. , Lis M. , Królikowski A.
• Konferencja: Computer Applications in Electrical Engineering 2014 (28-29.04.2014; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The article presents approach to implementation of random number generator on FPGA unit. The objective was to select a generator with good properties (correlation values and matching of probability density function were taken into account). Design focused on logical elements so that the pseudo-random number generation time depend only on the electrical properties of the system. The results are positive, because the longest time determining the pseudorandom number was 16.7ns for the “slow model” of the FPGA and 7.3ns for “fast model”, while one clock cycle lasts 20ns.

Słowa kluczowe

EN

random number generator; uniform noise; FPGA unit; logic functions

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2014
• Tom: No. 80
• Strony: 167--173
• Opis fizyczny: Bibliogr. 7 poz., tab.

Twórcy

autor

Kozierski P.

• Poznan University of Technology

autor

Lis M.

• Poznan University of Technology

autor

Królikowski A.

• Poznan University of Technology

Bibliografia

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