Finite-state State Machines Minimization by Using of Values of Input Variables at State Assignment

• Autorzy: Salauyou V. , Ostapczuk M.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we propose a method of FSM synthesis on field programmable gate arrays (FPGAs) when input variables are used for state assignment. For this purpose we offer a combined structural model of class A and class E FSMs. This paper also describes in detail algorithms for synthesis a class AE FSM which consists of splitting of internal states for performance of necessary conditions for synthesis of the class E FSM and state assignment of the class AE FSM. It is shown that the proposed method reduces the area for all families of FPGAs by a factor of 1.19…1.39 on average and by a factor of 3.00 for certain families.

Słowa kluczowe

EN

finite state machine (FSM); programmable gate array (FPGA); state assignment; area minimization; state splitting

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2017
• Tom: Vol. 63, No. 5
• Strony: 195--197
• Opis fizyczny: Bibliogr. 6 poz., rys., tab., wzory

Twórcy

autor

Salauyou V.

• Bialystok University of Technology, 45A Wiejska St., 15-351 Bialystok, Poland

autor

Ostapczuk M.

• Bialystok University of Technology, 45A Wiejska St., 15-351 Bialystok, Poland

Bibliografia

• [1] McCluskey E. J.: Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks. Information and Control, vol. 6, no. 2, pp. 99–118, 1963.
• [2] Pomeranz I., Cheng K. T.: STOIC: State Assignment Based on Output/Input Functions. IEEE Trans. on CAD, vol. 12, no. 8, pp. 613–622, 1993.
• [3] Forrest J.: ODE : Output Direct State Machine Encoding. In: European Design Automation Conference (EURO-DAC’95). pp. 600-605 Brighton. UK, 1995.
• [4] Solovjev V.: Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines. In: Euromicro Symposium on Digital Systems Design (DSD’2001), pp. 170-173, Warsaw, Poland, 2001.
• [5] Solov’ev V. V.: Minimization of Mealy Finite-State Machines by Using the Values of the Output Variables for State Assignment. Journal of Computer and Systems Sciences International, vol. 56, no. 1, pp. 96–104, 2017.
• [6] Yang S.: Logic synthesis and optimization benchmarks user guide. Version 3.0. Microelectronics Center of North Carolina (MCNC), North Carolina, USA, 1991.

Uwagi

EN

The present study was supported by a grant S/WI/1/2013 from Bialystok University of Technology and founded from the resources for research by Ministry of Science and Higher Education.

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).