Analogue CMOS ASICs in image processing systems

• Autorzy: Jendernalik W. , Blakiewicz G. , Handkiewicz A. , Melosik M.
• Języki publikacji: EN

Abstrakty

EN

In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

Słowa kluczowe

EN

analog CMOS circuits; early vision processing; switched current filters

• Wydawca: Komitet Metrologii i Aparatury Naukowej PAN
• Czasopismo: Metrology and Measurement Systems
• Rocznik: 2013
• Tom: Vol. 20, nr 4
• Strony: 613--622
• Opis fizyczny: Bibliogr. 39 poz., rys., wykr.

Twórcy

autor

Jendernalik W.

• Gdansk University of Technology, Department of Microelectronic Systems, Narutowicza 11/12, 80-233 Gdansk, Poland

autor

Blakiewicz G.

• Gdansk University of Technology, Department of Microelectronic Systems, Narutowicza 11/12, 80-233 Gdansk, Poland

autor

Handkiewicz A.

• Poznan University of Technology, Department of Computer Science, Piotrowo 3a, 60- 965 Poznan, Poland

autor

Melosik M.

• Poznan University of Technology, Department of Computer Science, Piotrowo 3a, 60- 965 Poznan, Poland

Bibliografia

• [1] Elouardi, A., Bouaziz, S., Dupret et al. (2008). A Smart Architecture for Low-Level Image Computing. Int. Journal of Computer Science and Applications, 5(3a), 1-19.
• [2] Gamal, A. E., Eltoukhy, H. (May/June 2005). CMOS image sensors. IEEE Circuits & Devices Magazine, 6-20.
• [3] Ciuti, G., Menciassi, A., Dario, P. (2011). Capsule endoscopy: from current achievements to open challenges. IEEE Reviews in Biomedical Engineering, 4, 59-72.
• [4] Kim, T. S., Song, S. Y., Jung, H., Kim, J., Yoon, E. S. (2007). Micro Capsule Endoscope for Gastro Intestinal Tract. Proc. of the 29th Annual International Conference of the IEEE EMBS.
• [5] Chen, X., Zhang, X., et al. (2009). A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC. IEEE Trans. Biomedical Circuits Syst., 3(1), 11-22.
• [6] Dubois, J., Ginhac, D., Paindavoine, M., Heyrman, B. (2008). A 10 000 fps CMOS Sensor With Massively Parallel Image Processing. IEEE J. Solid-State Circuits, 43(3), 706-717.
• [7] Higgins, Ch. M., Deutschmann, R. A., Koch, Ch. (1999). Pulse based 2 D motion sensor. IEEE Trans. Circuits Syst. II, 46(6), 677-687.
• [8] Gruev, V., Etienne-Cummings, R. (2002). Implementation of Steerable Spatiotemporal Image Filters on the Focal Plane. IEEE Trans. Circuits Syst. II, 49(4), 233-244.
• [9] Massari, N., Gottardi, M., et al. (2005). A CMOS Image Sensor With Programmable Pixel Level Analog Processing. IEEE Trans. Neural Netw., 16(6), 1673-1684.
• [10] Takahashi, N., Fujita, K., Shibata, T. (2009). A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensor. IEEE Trans. Circuits Syst. I, 56(11), 2384-2392.
• [11] Elouardi, A., Bouaziz, S., Dupret, A., et al. (2007). Image Processing Vision Systems: Standard Image Sensors Versus Retinas. IEEE Trans. Instrum. Meas., 56(5), 1675-1687.
• [12] Nilchi, A., Aziz, J., Genov, R. (2009). Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. IEEE J. Solid-State Circuits, 44(6), 1829-1839.
• [13] Lin, Z., Hoffman, M. W., Schemm, N., Leon Salas, W. D., Balkir, S. (2008). A CMOS Image Sensor for Multi Level Focal Plane Image Decomposition. IEEE Trans. Circuits Syst. I, 55(9), 2561-2572.
• [14] Njuguna, R., Gruev, V. (2010). Linear Current Mode Image Sensor Width Focal Plane Spatial Image Processing. Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 4265-4268.
• [15] Liñán Cembrano, G., Rodríguez-Vázquez, A., Carmona Galan, R., et al. (2004). A 1000 FPS at 128 × 128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), 1044-1055.
• [16] Etienne-Cummings, R., Kevork Kalayjian, Z., Cai, D. (2001). A Programmable Focal-Plane MIMD Image Processor Chip. IEEE J. Solid-State Circuits, 36(1), 64-73.
• [17] Lopich, A., Dudek, P. (2011). A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I, 58(10), 2420-2431.
• [18] Lopich, A., Dudek, P. (2008). ASPA: Focal Plane digital processor array with asynchronous processing capabilities. Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1592-1595.
• [19] Zarandy, A. (2011). Focal-Plane Sensor-Processor Chips. Chapter - Anatomy of the Focal-Plane Sensor-Processor Arrays. Springer.
• [20] Handkiewicz, A., Łukowiak, M., Kropidłowski, M. (2002). Switched-current implementation of two-dimensional DCT for image processing. 15th Annual IEEE Int. Conf. on ASIC/SOC, 186-190.
• [21] Handkiewicz, A., Kropidłowski, M., Łukowiak, M., Bartkowiak, M. (2000). Switched-current filter design for image processing systems. 13th Annual IEEE International Conference on ASIC/SOC, 8-12.
• [22] Handkiewicz, A., Kropidłowski, M., Łukowiak, M. (1999). Switched-Current Technique for Video Compression and Quantization. 12th Annual IEEE International Conference on ASIC/SOC, 299-303.
• [23] Marku, J., Koskinen, L., Paasio, A. (2007). A 130 nm Implementation of Analog Variable Block-Size Motion Estimation Cell. IEEE Int. Symp. on Integrated Circuits (ISIC-2007), 57-60.
• [24] McIlrath, L. G. (2000). A Low-Power Analog Correlation Processor for Real-Time Camera Aligment and Motion Computation. IEEE Trans. Circuits Syst. II, 47(12), 1353-1364.
• [25] Panovic, M., Demosthenous, A. (2006). A Low-Power Analog Motion Estimation Processor for Digital Video Coding. IEEE J. Solid-State Circuits, 41(3), 673-683.
• [26] Njuguna, R., Gruev, V. (2010). Linear Current Mode Image Sensor Width Focal Plane Spatial Image Processing. Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 4265-4268.
• [27] Jendernalik, W., Blakiewicz, G., Jakusz, J., Szczepański, S., Piotrowski, R. (2013). An Analog Sub-Miliwatt CMOS Image Sensor with Pixel-Level Convolution Processing. IEEE Trans. Circuits Syst. I, 60(2), 279-289.
• [28] Dudek, P., Hicks, P. J. (2005). A general-purpose processor-per-pixel analogue SIMD vision chip. IEEE Trans. Circuits Syst. I, 52(1), 13-20.
• [29] Jendernalik, W., Jakusz, J., Blakiewicz, G., et al. (2011). Analog CMOS processor for early vision processing with highly reduced power consumption. 20th European Conf. on Circuits Theory and Design (ECCTD), 745-748.
• [30] Jakusz, J., Jendernalik, W., Blakiewicz, G., et al. (2011). Ultra low power analogue CMOS vision chip. Przegląd Elektrotechniczny, 10, 88-91.
• [31] Jendernalik, W., Jakusz, J., Blakiewicz, G., et al. (2011). Ultra low power CMOS analogue processor for early vision processing. KKE’2011, cd-rom.
• [32] Jendernalik, W., Jakusz, J., Blakiewicz, G., et al. (2011). CMOS realisation of analogue processor for early vision processing. Bull. Polish Academy of Sciences Tech. Sci., 59(2), 141-147.
• [33] Jendernalik, W., Jakusz, J., Blakiewicz, G., Piotrowski, R. (2010). CMOS realisation of analogue processor for early vision processing. KKE’2010, cd-rom.
• [34] Blakiewicz, G. (2009). Analog multiplier for a low-power integrated image sensor. MIXDES’09, 226-229.
• [35] Handkiewicz, A. (1991). Two-dimensional switched capacitor filter design system for real-time image processing. IEEE Trans. Circ. Syst. for Video Technology, 1(3), 241-246.
• [36] Katarzynski, P., Melosik, M., Handkiewicz, A. (2013). gC-Studio - the environment for automated filter design. To be published in Bull. Polish Academy of Sciences Tech. Sci., 60(2).
• [37] Szczęsny, Sz., Naumowicz, M., Handkiewicz, A. (2012). SI-Studio - environment for SI circuits design automation. Bull. Polish Academy of Sciences Tech. Sci., 60(4), 757-762.
• [38] Rudnicki, R., Kropidłowski, M., Handkiewicz, A. (2010). Low power switched-current circuits with low sensitivity to the rise/fall time of the clock. Int. J. Circuit Theory and Applications, 38(5), 471-486.
• [39] Lopich, A., Dudek, P. (2011). Architecture and Design of a Programmable 3D-Integrated Cellular Processor Array for Image Processing. IFIP/IEEE Int. Conf. Very Large Scale Integration, VLSI-Soc 2011.