Minimum logic depth modulo 2n+1 adders

• Autorzy: Biernat J. , Jabłoński J.
• Języki publikacji: EN

Abstrakty

EN

The propagation of re-entrant carry reduces the speed of modulo 2n+1 addition. Two efficient solutions known to date rely on parallel generation of carries in prefix structures. The TPP is a modified parallel-prefix adder. The ELMMA adder utilizes the idea of parallel updating of sum bits due to carry propagation. The architecture of modulo 2n+1 adder of the less logic depth than the TPP and ELMMA designs and thus potentially faster is proposed.

Słowa kluczowe

EN

Residue Number System; modulo 2n+1 addition; parallel-prefix adders

• Wydawca: Komisja Informatyki Polskiej Akademii Nauk, Oddział w Gdańsku
• Czasopismo: Metody Informatyki Stosowanej
• Rocznik: 2008
• Tom: nr 3 (Tom 16)
• Strony: 41--55
• Opis fizyczny: Bibliogr. 14 poz., rys., tab.

Twórcy

autor

Biernat J.

• Politechnika Wrocławska, Instytut Informatyki, Automatyki i Robotyki

autor

Jabłoński J.

• Uniwersytet Zielonogórski, Wydział Matematyki i Ekonometrii

Bibliografia

• [1] Zimmerman R. Binary Adder Architectures for Cell-Based VLSI and their Synthesis. Hartung Gorre Verlag, 1998 (PhD dissertation, ETH Zurich 1997).
• [2] Cao B., Chang C-H., Srikanthan T. An efficient reverse converter for the 4-moduli set (2n–1,2n,2n+1,22n+1) based on the new Chineese Remainder Theorem. IEEE Trans. Circuits Syst., vol. 50, s. 1296-1303, Oct. 2003.
• [3] Beuchat J.-L., A Family of Modulo (2n+1) Multipliers. LIP Research Report 2004-39, Sept. 2004.
• [4] Zimmerman R. Efficient VLSI Implementation of Modulo (2n±1) Addition and Multiplication. Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia 1999, pp. 158-167.
• [5] Hiasat A. A. High-speed and reduced-area modular structures for RNS. IEEE Trans. Comput., vol. 51, no. 1, pp. 84-89, Jan. 2002.
• [6] Efstathiou C., Vergos H. T., Nikolos D. Modulo 2n+1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers, vol. 52, no. 11, pp. 1399-1406, Nov. 2003.
• [7] Efstathiou C., Vergos H. T., Nikolos D. Fast Parallel-Prefix Modulo 2n+1 Adders. IEEE Trans. Computers, vol. 53, no. 9, pp. 1211-1216, Sep. 2004.
• [8] Keliher T. P., Owens R. M., Irwin M. J., Hwang T.-T. ELM – A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Comput., vol. 41, no. 9, pp. 1181–1184, Sep. 1992.
• [9] Patel R. A., Benaissa M., Boussakta S., Powell N. Power-delay-area efficient modulo 2n+1 adder architecture for RNS. Electronics Letters, 3rd March 2005, vol. 41, no. 5, pp. 231-232.
• [10] Koren I. Computer Arithmetic Algorithms. Natick Mass. A K Peters, 2002 (2nd ed.).
• [11] Brent R. P., Kung H. T. A Regular Layout for Parallel Adders. IEEE Trans. Computers, vol. 31, no. 3, pp. 260–264, Mar. 1982.
• [12] Vergos H. T., Efstathiou C., Nikolos D. Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers, vol. 51, no. 12, pp. 1389-1399, Dec. 2002.
• [13] Jabłonski J., Biernat J. Fast residue generators for moduli set 2k±1. Proc. 11th Int. Electrotechnical and Computer Science Conference, ERK 2002, pp. 51–54.
• [14] Kalampouskas L., Nikolos D., Efstathiou C., Vergos H. T., Kalamantianos J. High-Speed Parallel-Prefix Modulo 2n–1 Adders. IEEE Trans. Computers, vol. 49, no. 7, pp. 673-680, July 2000.