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Low Leakage and Robust Sub-threshold SRAM Cell Using Memristor

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) subthreshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared.
Rocznik
Strony
667--676
Opis fizyczny
Bibliogr. 35 poz., rys., tab., wykr.
Twórcy
  • Jamia Milia Islamia Central University, India
  • Jamia Milia Islamia Central University, India
  • Jamia Milia Islamia Central University, India
Bibliografia
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  • [3] S. S. Sarwar, S. A. N. Saqueb, F. Quaiyum and A. B. M. H. Rashid, "Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design," in IEEE Access, vol. 1, pp. 29-34, 2013, https://doi.org/10.1109/ACCESS.2013.2259891.
  • [4] Saminathan V, Paramasivam K. Design and analysis of low power hybrid memristor-CMOS based distinct binary logic nonvolatile SRAM cell. Circuits and Systems. 2016 Mar 23;7(3):119-27. https://doi.org/10.4236/cs.2016.73012.
  • [5] Soeleman, H. and Roy, K., 2000, March. Digital CMOS logic operation in the sub-threshold region. In Proceedings of the 10th great lakes symposium on VLSI (pp. 107-112). https://doi.org/10.1145/330855.331014.
  • [6] Calhoun, Benton H., Alice Wang, Naveen Verma, and Anantha Chandrakasan. "Sub-threshold design: the challenges of minimizing circuit energy." In Proceedings of the 2006 international symposium on Low power electronics and design, pp. 366-368. ACM, 2006. https://doi.org/10.1145/1165573.1165661.
  • [7] B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation," in IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 680-688, March 2007, https://doi.org/10.1109/JSSC.2006.891726.
  • [8] Seo, Hae-Jun, Dong-keun Song, Ju-ho Lee, Mohamed G. Ahmed, and Tae-Won Cho. "A study on the memristor-based non-volatile 4T static RAM cell." In International Technical Conference on Circuits/Systems, Computers and Communications. 2011.
  • [9] G. Razavipour, A. Afzali-Kusha and M. Pedram, "Design and Analysis of Two Low-Power SRAM Cell Structures," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 10, pp. 1551-1555, Oct. 2009, https://doi.org/10.1109/TVLSI.2008.2004590.
  • [10] Feki, Anis, Bruno Allard, David Turgis, Jean-Christophe Lafont, and Lorenzo Ciampolini. "Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell." In 2012 International SoC Design Conference (ISOCC), pp. 470-474. IEEE, 2012.
  • [11] A. Islam and M. Hasan, "Leakage Characterization of 10T SRAM Cell," in IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 631-638, March 2012, https://doi.org/10.1109/TED.2011.2181387.
  • [12] Tae-Hyoung Kim, Jason Liu, J. Keane and C. H. Kim, "Circuit techniques for ultra-low power subthreshold SRAMs," 2008 IEEE International Symposium on Circuits and Systems, 2008, pp. 2574-2577, https://doi.org/10.1109/ISCAS.2008.4541982.
  • [13] Islam, Aminul, Mohd Hasan, and Tughrul Arslan. "Variation resilient subthreshold SRAM cell design technique." International Journal of Electronics 99, no. 9 (2012): 1223-1237. https://doi.org/10.1080/00207217.2012.669708.
  • [14] A. R. Ramani and K. Choi, "A novel 9T SRAM design in sub-threshold region," 2011 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 2011, pp. 1-6, https://doi.org/10.1109/EIT.2011.5978615.
  • [15] B. Zhai, S. Hanson, D. Blaauw and D. Sylvester, "A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM," in IEEE Journal of Solid-State Circuits, vol. 43, no. 10, pp. 2338-2348, Oct. 2008, https://doi.org/10.1109/JSSC.2008.2001903.
  • [16] B. Zeinali, J. K. Madsen, P. Raghavan and F. Moradi, "Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power," 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 74-79, https://doi.org/10.1109/ISVLSI.2015.73.
  • [17] W. Wei, K. Namba, J. Han and F. Lombardi, "Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation," in IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 905-916, Sept. 2014, https://doi.org/10.1109/TNANO.2014.2329915.
  • [18] Yang, J. Joshua, Matthew D. Pickett, Xuema Li, Douglas AA Ohlberg, Duncan R. Stewart, and R. Stanley Williams. "Memristive switching mechanism for metal/oxide/metal nanodevices." Nature nanotechnology 3, no. 7 (2008): 429.
  • [19] N. S. M. Hadis, A. A. Manaf, S. H. Herman and S. H. Ngalim, "High Roff/Ron ratio liquid based memristor sensor using sol gel spin coating technique," 2015 IEEE SENSORS, 2015, pp. 1-4, https://doi.org/10.1109/ICSENS.2015.7370379.
  • [20] K. Eshraghian, K. Cho, O. Kavehei, S. Kang, D. Abbott and S. S. Kang, "Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1407-1417, Aug. 2011, https://doi.org/10.1109/TVLSI.2010.2049867.
  • [21] Louis, V. Jeffry, and Jai Gopal Pandey. "A Novel Design of SRAM Using Memristors at 45 nm Technology." In International Symposium on VLSI Design and Test, pp. 579-589. Springer, Singapore, 2019. https://doi.org/10.1007/978-981-32-9767-8_48.
  • [22] Biolek, Zdeněk, Dalibor biolek, and Viera biolkova. "SPICE Model of Memristor with Nonlinear Dopant Drift." Radioengineering 18, no. 2 (2009).
  • [23] biolek, dalibor, massimiliano di ventra, and yuriy v. pershin. "Reliable SPICE simulations of memristors, memcapacitors and meminductors."Radioengineering, vol. 22, no. 4, pp. 945-968, 2013.
  • [24] S. P. Adhikari, M. P. Sah, H. Kim and L. O. Chua, "Three Fingerprints of Memristor," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 11, pp. 3008-3021, Nov. 2013, https://doi.org/10.1109/TCSI.2013.2256171.
  • [25] Bikki, Pavankumar, and Pitchai Karuppanan. "SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey." Circuits and Systems 8, no. 02 (2017): 23.
  • [26] Reddy, M. Madhusudhan, M. Sailaja, and K. Babulu. "Low-power SRAM cell for efficient leakage energy reduction in deep submicron using 0.022 μm CMOS technology." ARPN Journal of Engineering and Applied Sciences 13 (2018): 1443-1452.
  • [27] islam, aminul, and mohd hasan. "Variability analysis of 6t and 7t sram cell in sub-45nm technology." IIUM Engineering Journal 12, no. 1 (2011): 13-30. https://doi.org/10.31436/iiumej.v12i1.25.
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  • [30] wei wang, aaron gibby, zheng wang, tze wee chen, shinobu fujita, peter griffin, yoshio nishi, and simon wong “Nonvolatile SRAM Cell”, IEDM Tech. Dig., 2006, pp. 1-4. https://doi.org/10.1109/IEDM.2006.346730.
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  • [32] P. Chiu et al., "Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications," in IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1483-1496, June 2012, https://doi.org/10.1109/JSSC.2012.2192661.
  • [33] Ho, Patrick WC, Haider Abbas F. Almurib, and T. Nandha Kumar. "Memristive SRAM cell of seven transistors and one memristor." Journal of Semiconductors 37, no. 10 (2016): 104002.
  • [34] Pal S, Reddy MS, Islam A. Variation-tolerant sub-threshold SRAM cell design technique, ARPN Journal of Engineering and Applied Sciences, vol. 10, no. 8, may 2015.
  • [35] Makosiej, Adam, Giorgio Palma, Jean-Michel Portal, Marc Bocquet, Olivier Thomas, Fabien Clermidy, Marina Reyboz et al. "Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up." Solid-state electronics 90 (2013): 99-106.
Uwagi
Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-0f9e7bbb-1273-484e-a844-1ddc4fecffbd
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