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The First Step Toward Processor for Rough Set Methods

Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In this paper we propose a combination of capabilities of the FPGA based device and PC computer for data processing using rough set methods. Presented architecture has been tested on the exemplary data sets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.
Wydawca
Rocznik
Strony
429--443
Opis fizyczny
Bibliogr. 21 poz., tab., wykr.
Twórcy
autor
  • Faculty of Computer Science, Bialystok University of Technology, Wiejska 45A, 15-351 Bialystok, Poland
  • Faculty of Computer Science, Bialystok University of Technology, Wiejska 45A, 15-351 Bialystok, Poland
autor
  • Faculty of Computer Science, Bialystok University of Technology, Wiejska 45A, 15-351 Bialystok, Poland
Bibliografia
  • [1] P. Athanas, D. Pnevmatikatos, N. Sklavos (Eds.), Embedded Systems Design with FPGAs, Springer, 2013.
  • [2] A. Kanasugi, A. Yokoyama, A basic design for rough set processor, In The 15th Annual Conference of Japanese Society for Artificial Intelligence, 2001.
  • [3] A. Kanasugi, A design of architecture for rough set processor, JSAI2001 Workshops, LNAI2253, SpringerVerlag, 2001, pp. 406-412.
  • [4] A. Kanasugi, M. Matsumoto, Design and implementation of rough rules generation from logical rules on FPGA board, RSEISP 2007, LNAI 4585, Springer-Verlag, 2007, pp. 594-602.
  • [5] S. Kilts, Advanced FPGA Design: Architecture, Implementation, and Optimization, Wiley-IEEE Press, 2007.
  • [6] M. Kopczynski, J. Stepaniuk: Rough set methods and hardware implementations, Zeszyty Naukowe Politechniki Białostockiej. Informatyka Zeszyt 8, 2011, pp. 5-18.
  • [7] M. Kopczynski, J. Stepaniuk: Hardware Implementations of Rough Set Methods in Programmable Logic Devices, Rough Sets and Intelligent Systems - Professor Zdzisław Pawlak in Memoriam, eds. Andrzej Skowron, Zbigniew Suraj, Intelligent Systems Reference Library 43, Heidelberg, Springer, 2013, pp. 309-321
  • [8] T. Lewis, M. Perkowski, L. Jozwiak, Learning in Hardware: Architecture and Implementation of an FPGA- Based Rough Set Machine, euromicro, vol. 1, 25th Euromicro Conference (EUROMICRO ’99)-Volume 1, 1999, pp. 1326.
  • [9] M. Muraszkiewicz, H. Rybinski, Towards a Parallel Rough Sets Computer In: Rough Sets, Fuzzy Sets and Knowledge Discovery, Springer-Verlag, 1994, pp. 434-443.
  • [10] M. Muraszkiewicz, Sieci komórkowe do przetwarzania danych nienumerycznych, Prace IINTE, no. 52, 1984.
  • [11] Z. Pawlak, Elementary rough set granules: Toward a rough set processor. In: S. K. Pal, L. Polkowski, and A. Skowron, editors, Rough-Neurocomputing: Techniques for Computing with Words, Cognitive Technologies. Springer-Verlag, Berlin, Germany, 2004, pp. 5-14.
  • [12] Z. Pawlak, A. Skowron, Rudiments of rough sets. Information Sciences, 177(1) 2007, pp. 3-27.
  • [13] W. Pedrycz, A. Skowron, V. Kreinovich (Eds.), Handbook of Granular Computing, John Wiley & Sons, New York 2008.
  • [14] L. Sekanina, Evolvable hardware, Handbook of Natural Computing, Springer, 2012, pp. 1657-1705.
  • [15] A. Skowron, C. Rauszer, The discemibility matrices and functions in information systems, in: R. Slowinski (Ed.), Intelligent Decision Support, Handbook of Applications and Advances of the Rough Sets Theory, Kluwer, Dordrecht, 1992, 331-362.
  • [16] A. Skowron, J. Stepaniuk, Tolerance Approximation Spaces, Fundamenta Informaticae, vol. 27, no. 2-3, 1996, pp. 245-253.
  • [17] J. Stepaniuk, Rough-Granular Computing in Knowledge Discovery and Data Mining, Springer, 2008.
  • [18] T. Strakowski, H. Rybinski, A Distributed Decision Rules Calculation Using Apriori Algorithm, T. Rough Sets 11, 2010, pp. 161-176.
  • [19] G. Sun, X. Qi, Y. Zhang, A FPGA-based implementation of Rough Set Theory, Control and Decision Conference (CCDC), 2011 Chinese, pp. 2561-2564, 23-25 May 2011 doi: 10.1109/CCDC.2011.5968642.
  • [20] Altera Corporation, www.altera.com, cited August 14, 2013.
  • [21] Xilinx Corporation, www.xilinx.com, cited August 14, 2013.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-0f700dea-cc55-4180-8cce-2de2b974d49e
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