Design optimisation of the deep trench termination for superjunction power devices

• Autorzy: Noblecourt S. , Morancho F. , Isoird K. , Austin P. , Tasselli J.
• Języki publikacji: EN

Abstrakty

EN

Among the numerous solutions developed to improve the voltage handling capability of superjunction power devices, the Deep Trench Termination (DT²) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of TCAD 2D and 3D-simulations allowing the realization of deep trench superjunction devices (diodes and MOS transistors) for 1200 V applications. The work is focused on the influence of the dielectric passivation layer thickness and the field plate length on the breakdown voltage of a DT-SJDiode.

Słowa kluczowe

EN

deep trench termination; field plate; superjunction; breakdown voltage

PL

superjunction; napięcie przebicia

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2015
• Tom: Vol. 6, nr 4
• Strony: 117--123
• Opis fizyczny: Bibliogr. 11 poz., il. (w tym kolor.), wykr.

Twórcy

autor

Noblecourt S.

• Université de Toulouse and CNRS-LAAS, Toulouse, France

autor

Morancho F.

• Université de Toulouse and CNRS-LAAS, Toulouse, France

autor

Isoird K.

• Université de Toulouse and CNRS-LAAS, Toulouse, France

autor

Austin P.

• Université de Toulouse and CNRS-LAAS, Toulouse, France

autor

Tasselli J.

• CNRS-LAAS, Toulouse, France

Bibliografia

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• [2] M. Sagio, D. Fagone, S. Musumeci, “MDMESH™: innovative technology for high voltage power MOSFETs”, ISPSD’2000, pp. 65-68.
• [3] K. Takahashi et al., “20mficm2 660V Super Junction MOSFETs fabricated by Deep Trench Etching and Epitaxial Growth”, ISPSD 2006, pp. 1-4.
• [4] L. Théolier, H. Mahfoz-Kotb, K. Isoird, F. Morancho, “A new junction termination technique: the Deep Trench Termination (DT2)”, ISPSD 2009, pp. 176-179.
• [5] R. Miao, F. Lu, Y. Wing, D. Wei, “Deep oxide trench termination structure for super-junction MOSFET”, Electronics letters, vol. 47, n°16 2012.
• [6] K. Seto, R. Kamibaba, M. Tsukuda, I. Omura, “Universal Trench Edge Termination Design,” ISPSD 2012, pp.161-164.
• [7] T. Fujihira, “Theory of semiconductor superjunctions devices”, Japanese Journal of Applied Physics, Vol. 36, pp. 6254-6262, 1997.
• [8] S. Nizou, et al., “Deep Trench doping by plasma immersion ion implantation in silicon”, 16th International conference on Ion Implantation Technology 2006, Marseille, pp. 229-232, 11-16 June 2006.
• [9] Dow Chemical Company Processing for CYCLOTENE 4000 Series Photo BCB Resins, Febrary 2005.
• [10] S. Noblecourt et al., “Design and realization of 600 V DT-SJDiode”, European Journal of Electrical Engineering, Vol.17, N°5-6/2014 pp. 345-361.
• [11] S. C. Sun, “Physics and technology of power MOSFET’s”, Ph. D Thesis, Standford University, 1982.