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SPICE simulation of passive N-type guard rings in smart power ICs

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Języki publikacji
EN
Abstrakty
EN
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a SPICE-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our approach consists in integrating a new substrate model in SPICE to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.
Twórcy
autor
  • Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
  • Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
  • Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
autor
  • Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
Bibliografia
  • [1] Joseph Briaire and KS Krisch. Principles of substrate crosstalk generation in CMOS circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(6):645–653, 2000.
  • [2] RB Merrill, WM Young, and Kevin Brehmer. Effect of substrate material on crosstalk in mixed analog/digital integrated circuit. In International Electron Devices Meeting, pages 433–436. IEEE, 1994.
  • [3] Maher Kayal, Richard Lara Saez, and Marc Pastre. The reduction of switching noise using CMOS current steering logic. In Substrate Noise Coupling in Mixed-Signal ASICs, pages 209–232. Springer, 2003.
  • [4] Zhe Wang, Rajeev Murgai, and Jaijeet Roychowdhury. ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(1):56–64, 2005.
  • [5] Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, and Koichiro Ishibashi. An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal Socs. IEEE Journal of Solid-State Circuits, 40(1):67–79, 2005.
  • [6] Kozo Sakamoto, Yasuhiro Nunogawa, Kohichiro Satonaka, Toyomasa Kouda, and Shuichi Horiuchi. An intelligent power ic with reverse battery protection for fast-switching high-side solenoid drive. IEEE Transactions on Electron Devices, 46(8):1775–1781, 1999.
  • [7] Michael Schenkel. Substrate current formation, effects, and protection strategies. Analog Circuit Design: High-Speed AD Converters, Automotive Electronics and Ultra-Low Power Wireless, 15:151, 2006.
  • [8] O Gonnard, G Charitat, Ph Lance, E Stefanov, M Suquet, M Bafleur, N Mauran, and A Peyre-Lavigne. Substrate current protection in smart power IC’s. In The 12th International Symposium on Power Semiconductor Devices and ICs, pages 169–172. IEEE, 2000.
  • [9] Thomas KH Starke, Paul M Holland, Shahzad Hussain, WM Jamal, PA Mawby, and Petar M Igic. Highly effective junction isolation structures for pics based on standard cmos process. IEEE Transactions on Electron Devices, 51(7):1178–1184, 2004.
  • [10] Steven H Voldman, Charles Nicholas Perez, and Anne Watson. Guard rings: theory, experimental quantification and design. In Electrical Overstress/Electrostatic Discharge Symposium, pages 1–10. IEEE, 2005.
  • [11] Bruno Murari, Franco Bertotti, and Guiovanni A Vignola. Smart power ICs: technologies and applications, volume 6. Springer Science & Business Media, 2002.
  • [12] Fabrizio Lo Conte, J-M Sallese, Marc Pastre, Franc¸ois Krummenacher, and Maher Kayal. Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates. IEEE Transactions on Electron Devices, 57(1):263–272, 2010.
  • [13] Camillo Stefanucci, Pietro Buccella, Maher Kayal, and Jean-Michel Sallese. Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs. Solid-State Electronics, 105:21–29, 2015.
  • [14] RR Troutman. Epitaxial layer enhancement of n-well guard rings for CMOS circuits. IEEE electron device letters, 4(12):438–440, 1983.
  • [15] Alan Hastings. The art of analog layout. Prentice Hall, 2006. [16] Michael Kollmitzer, Markus Olbrich, and Erich Barke. Analysis and modeling of minority carrier injection in deep-trench based BCD technologies. In 9th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), pages 245–248. IEEE, 2013.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-0e027d4f-f643-4fc6-b16f-e5d45aa4f3a3
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