A MUX based signed-floating-point MAC architecture using UCM algorithm

• Autorzy: Sarma R. , Bhargava C. , Jain S.

Identyfikatory

DOI

10.24425/bpasts.2020.134182

• Języki publikacji: EN

Abstrakty

EN

Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8x8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of – (7.96875)10 to +(7.96875)10. The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.

Słowa kluczowe

EN

floating-point MAC; UCM; cadence; TSMC 130 nm; GPDK 90 nm

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2020
• Tom: Vol. 68, nr 4
• Strony: 835--844
• Opis fizyczny: Bibliogr. 31 poz., rys., tab.

Twórcy

autor

Sarma R.

• VLSI Design, SEEE, Lovely Professional University, GT Road, Phagwara, Punjab, India

autor

Bhargava C.

• VLSI Design, SEEE, Lovely Professional University, GT Road, Phagwara, Punjab, India

autor

Jain S.

• Department of Electronics and Communication Engineering, Waknaghat, Solan, HP, India

Bibliografia

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Uwagi

PL

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).