High-speed binary-to-residue converter design using 2-bit segmentation of the input word

• Autorzy: Smyk Robert , Czyżak Maciej

Identyfikatory

DOI

10.26408/124.04

• Języki publikacji: EN

Abstrakty

EN

In this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented by each segment, the modulo m reduction using a segment modulo m generator is performed. The use of 2-bit segments substantially reduces the hardware amount of the layer of input modulo m generators. The generated residues are added using the multi-operand modulo m adder based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to the 2m range and fast two-operand modulo m additions. Hardware amount and time delay analyses are also included.

Słowa kluczowe

EN

binary-to-residue conversion; residue number system; FPGA

• Wydawca: Publishing House of Gdynia Maritime University
• Czasopismo: Scientific Journal of Gdynia Maritime University
• Rocznik: 2022
• Tom: nr 124
• Strony: 42--56
• Opis fizyczny: Bibliogr. 14 poz., rys., tab.

Twórcy

autor

Smyk Robert

• Gdańsk University of Technology, 11/12 Gabriela Narutowicza Street, 80-233 Gdańsk, Poland

• https://orcid.org/0000-0001-9365-4633

autor

Czyżak Maciej

• The University of Applied Sciences in Elbląg, 1 Wojska Polskiego Street, 82-300 Elbląg, Poland

• https://orcid.org/0000-0002-2249-1619

Bibliografia

• 1. Alia, G., Martinelli, E., 1990, Short Note: VLSI Binary-Residue Converters for Pipelined Processing, The Computer Journal, Vol. 33, No. 5, pp. 473–475.
• 2. Avižienis, A., 1964, A Set of Algorithms for a Diagnosable Arithmetic Unit, Jet Propulsion Laboratory, California Institute of Technology, USA.
• 3. Avižienis A., 1971, Arithmetic Codes: Cost and Effectiveness Studies for Applications in Digital System Design, IEEE Trans. Comput., Vol. C-20, pp. 1322–1331.
• 4. Cardarilli, G.C., Nannarelli, A., Re, M., 2007, Residue Number System for Low-power DSP Applications, Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, IEEE, pp. 1412–1416.
• 5. Czyżak, M., 2004, High-Speed Binary-to-Residue Converter with Improved Architecture, 27th International Conference on Fundamentals of Electrotechnics and Circuit Theory, Gliwice-Niedzica, pp. 431–436.
• 6. Czyżak, M., 2013, Digital Structures for High-Speed Signal Processing, Politechnika Gdańska, pp. 94–95.
• 7. Czyżak, M., Smyk R., 2008, High-Speed FPGA Pipelined Binary-to-Residue Converter, Poznan University of Technology, Academic Journals Electrical Engineering, No. 58, pp. 65–72.
• 8. Huang, K., 1979, Computer Arithmetic: Principles, Architecture, and Design, John Wiley & Sons.
• 9. Luan, Z., Chen, X., Ge, N., Wang, Z., 2014, Simplified Fault-Tolerant FIR Filter Architecture Based on Redundant Residue Number System, Electronics Letters, Vol. 50, No. 23, pp. 1768–1770.
• 10. Miller, D.D., Altschul, R.E., King, J.R., Polky, J.N., 1986, Analysis of the Residue Class Core Function of Akushskii, Burcev, and Pak. In Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, pp. 390–401.
• 11. Piestrak, S.J., 1994a, Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem, Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 508–511.
• 12. Piestrak, S.J., 1994b, Design of Residue Generators and Multioperand Modulo Adders Using Carry-Save Adders, IEEE Trans. Comp., Vol. 43, pp. 68–77.
• 13. Premkumar, A.B., 2002, A Formal Framework for Conversion from Binary to Residue Numbers, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 2, pp. 135–144.
• 14. Szabo, N.S., Tanaka, R.J., 1967, Residue Arithmetic and its Applications to Computer Technology, New York, McGraw-Hill.

Uwagi

Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).