Identyfikatory
DOI
Warianty tytułu
Języki publikacji
Abstrakty
The goal of the paper was to shorten the calculation time by realising all used signal processing algorithms in the form of stack filters. The architecture of these filters allows us to process signals using the advantages of hardware processing and simultaneous signal processing. This paper elaborated on the synthesis of stack filters which realise median, averaging, opening and closing operations. The novel achievement was to develop the binary box method which allows us to obtain stack filters for more complex algorithms. This method consists of two stages and requires that we construct a spatial structure of the data. This structure allows us to examine the stacking property in two steps. Obtained in this way architecture of the function is predisposed to VLSI implementation. The authors devised this method transforming the averaging filter into stack filter; however, the invented binary box method allows us to synthesise stack filter which realises more complex signal processing algorithms. The only assumption which limits the class of acceptable algorithms is the fact that the algorithm has to satisfy the stacking property at each stage of the signal processing. The proposed approach allows us to convert well-known signal processing algorithms into realisation which guarantees significantly greater speeds of signal processing.
Rocznik
Tom
Strony
193--208
Opis fizyczny
Bibliogr. 62 poz., rys., tab.
Twórcy
autor
- Silesian University of Technology, Institute of Automatic Control, 16 Akademicka St., Gliwice, Poland
autor
- Silesian University of Technology, Institute of Automatic Control, 16 Akademicka St., Gliwice, Poland
Bibliografia
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- [41] M.K. Prasad, “Stack filter design using selection probabilities”, IEEE Transactions on Signal Processing, Volume: 53, Issue: 3 Pages: 1025–1037, (2005).
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- [43] S. Guangming, S. Liya, L. Honghua, and H. Daojun, “Dynamic nonlinear threshold decomposition algorithm for implementing stack filters”, IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Volume:3, Pages: III – 641‒4, Vol. 3, (2004).
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- [48] A. Hiasat, O. Hasan, “Bit-serial architecture for rank order and stack filters”, Integration, the VLSI Journal archive, Volume 36 Issue 1‒2,Pages 3‒12, (2003).
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- [60] A. Kordecki, A. Bal, and H. Palus, “A smooth local polynomial model of vignetting”, 22nd International Conference on Methods and Models in Automation and Robotics (MMAR), DOI: 10.1109/MMAR.2017.8046944, August (2017).
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Uwagi
PL
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-0a97191c-582d-4f10-8b64-e06db47759fa