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Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier

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Języki publikacji
EN
Abstrakty
EN
The paper presents an original architecture and implementation of 9-bit Linearized Pulse Width Modulator (LPWM) for Class-BD amplifier, based on the hybrid method using STM32 microcontroller and Programmable Tapped Delay Line (PTDL). The analog input signals are converted into 12-bit PCM signals, then are directly transformed into 32-bit LBDD DPWM data of the pulse-edge locations within n-th period of the switching frequency, next requantized to the 9-bit digital outputs, and finally converted into the two physical trains of 1-bit PWM signals, to control the output stage of the Class-BD audio amplifier. The hybrid 9-bit quantizer converts 6 MSB bits using counter method, based on the peripherals of STM32 microcontroller, while the remaining 3 LSB bits - using a method based on the PTDL. In the paper extensive verification of algorithm and circuit operation as well as simulation in MATLAB and experimental results of the proposed 9-bit hybrid LBDD DPWM circuit have been performed. It allows to attain SNR of 80 dB and THD about 0,3% within the audio baseband.
Twórcy
  • Applied Sciences in Tarnow, Poland
  • Applied Sciences in Tarnow, Poland
Bibliografia
  • [1] S. M. Cox, Jun Yu, W. L. Goh, M. T. Tan, Intrinsic Distortion of a Fully Differential BD-Modulated Class-D Amplifier with Analog Feedback, IEEE Transactions on Circuits and Systems − I: Regular Papers 1, Vol. 60 , Iss. 1, pp. 1 – 11, Jan. 2013.
  • [2] M. Johansen, K. Nielsen, A Review and Comparison of Digital PWM Methods for Digital Pulse Modulation Systems., 107th AES Convention , 1999 September 24-27 New York.
  • [3] C. Pascual, Z. Song, P. T. Krein, et. al., High-Fidelity PWM Inverter for Digital Audio Amplification: Spectral Analysis, Real-Time DSP Implementation, and Results, IEEE Transactions on Power Electronics, Vol. 18, No. 1, January, 2003, pp. 474-485.
  • [4] A. Syed, E. Ahmed, D. Maksimovic, E. Alarcon, Digital pulse width modulator architectures, Proc. IEEE Power Electron. Spec. Conf., vol. 6, pp.4689-4695, 2004.
  • [5] R. Cellier, G. Pillonnet, A. Nagari, N. Abouchi, An Review of Fully Digital Audio Class D Amplifiers Topologies, Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop, June 28-July 1, 2009.
  • [6] V. Adrian, Bah-Hwee Gwee, J. S. Chang, A Review of Design Methods for Digital Modulators, 2007 IEEE International Symposium on Integrated Circuits (ISIC-2007).
  • [7] Ch. K. Lam, M. T. Tan, S. M. Cox, K. S. Yeo, Class-D Amplifier Power Stage With PWM Feedback Loop, IEEE Transactions On Power Electronics, Vol. 28, No. 8, pp. 3870 – 3881, August 2013.
  • [8] M. Berkhout, L. Dooper, Class-D Audio Amplifiers in Mobile Applications. IEEE Transactions On Circuits And Systems-I: Regular Papers, Vol. 57, No. 5, pp. 991-1002, May 2010
  • [9] J-W Jung, M. J. Hawksford, An Oversampled Digital PWM Linearization Technique for Digital-to-Analog Conversion, IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 51, No. 9, pp. 1781 – 1789, September 2004.
  • [10] S. R. Norsworthy, Optimal Nonrecursive Noise Shaping Filters For Oversampling Data Converters Part 1: Theory, Proc. of 1993 IEEE International Symposium on Circuits and Systems, 3-6 May 1993, Chicago, USA, IEEE Xplore: 06 August 2002.
  • [11] M. T. Pasha, M. F. U. Haque, J. Ahmad, T. Johansson, A Modified All-Digital Polar PWM Transmitter, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 2, pp. 758-768, Feb. 2018.
  • [12] St. W. Kuta, W. Kołodziejski, J. Jasielski, Hybrid LBDD Digital Pulse Width Modulator (DPWM) for Class-BD Audio Amplifiers, Science, Technology and Innovation, Vol. 1, No. 1, pp. 1 – 10, 2017.
  • [13] J. Jasielski, St. Kuta, W. Machowski, W. Kołodziejski, Hybrid DPWM implementation using coarse and fine programmable ADLL, ELSEVIER, Microelectronics Journal, Vol. 45, Iss. 9, pp. 1202-1211, September 2014.
  • [14] Bah-Hwee Gwee, J. S. Chang, H. Li, A Micropower Low-Distortion Digital Pulsewidth Modulator for a Digital Class D Amplifier, IEEE Transactions on Circuits and Systems—Ii: Analog and Digital Signal Processing, Vol. 49, No. 4, April 2002.
  • [15] H, Wang, M. Zhang, Y. Liu, High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip, Applied Sciences, January 2017, 7, pp. 1 – 11, 52.
  • [16] V. R. Kota, Hybrid Pulse Width Modulation Techniques for the Reduction of Switching Losses and Voltage Harmonics in Cascaded Multilevel Inverters, World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering , Vol.8, No.7, pp. 1195- 1200, 2014.
  • [17] Xuzhen Shen, Xiaobo Wu, and Jing Lu, Lin Qin, Hybrid DPWM with Analog Delay Locked Loop, Proceedings of the International MultiConference of Engineers and Computer Scientists 2010, Vol II, IMCS 2010 March 2010.
  • [18] Ch. Yan, Ch. Hu, J. Wu, A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA, Applied Sciences, July 2019, 9, pp. 1 – 12, 2705.
  • [19] https://www.st.com/ STM32F4 Reference Manual
  • [20] http://www.cornucopiaplastics.com/ 3-Bit Programmable FAST TTL Logic Delay Line
Uwagi
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).
Typ dokumentu
Bibliografia
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bwmeta1.element.baztech-08f314b2-9cd0-4387-96a5-9b9b5c4a0b3b
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