Reliable digital dead-time generator for the GaN HEMTs based H-bridge converters

• Autorzy: Svarny Jiri

Identyfikatory

DOI

10.24425/aee.2020.134629

• Języki publikacji: EN

Abstrakty

EN

The paper deals with hardware solution of a fully digital dead-time generator. The circuit is applicable to the H-bridges based on any type of semiconductor switching devices including SiC, IGBT, Si-MOSFET and up-to-date GaN HEMTs. The generation of dead-times is ensured by commercially available silicon delay lines. High temperature stability is obtained by self-compensation of propagation delay of logic elements thanks to the symmetry of design topology. The circuit can be set-up to generate dead-times in the range from 10 ns to 500 ns. Longer dead-times are also available by simple cascading of the silicon delay lines. The key motivation for development of the circuit was unavailability of ready to use integrated solutions on the market. Moreover, contrary to the other solutions the proposed circuit is immune to prospective oscillations of an input PWM signal. The paper brings a detailed analysis of the circuit principle, results of the verification of a sample solution and an example of practical application as well.

Słowa kluczowe

EN

dead-time generator; delay-line; GaN HEMTs; H-bridge driver

• Wydawca: Polish Academy of Sciences, Committee on Electrical Engineering
• Czasopismo: Archives of Electrical Engineering
• Rocznik: 2020
• Tom: Vol. 69, nr 4
• Strony: 781--792
• Opis fizyczny: Bibliogr. 13 poz., rys., tab., wz.

Twórcy

autor

Svarny Jiri

• Regional Innovation Centre for Electrical Engineering (RICE) University of West Bohemia Univerzitni 8, 306 14 Pilsen, Czech Republic

Bibliografia

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• [4] Texas Instruments Inc., LMG1205 80V, 1.2-A to 5-A, Half Bridge GaN Driver with Integrated Bootstrap Diode, Data Sheet, SNOSD37A (2018).
• [5] Texas Instruments Inc., LMG5200 80V, 10A GaN Half-Bridge Power Stage, Data Sheet, SNOSCY4E (2018).
• [6] Shi L. F., Liu F. B., He H. S., Mao X. Y., Lai X. Q., Design of adaptive dead-time control circuit for resonant half-bridge driver, International Journal of Electronic, vol. 100, no. 10, pp. 1317–1331 (2013).
• [7] Kao S. K., Wu J. H., Cheng H. C., All-digital controlled boost DC-DC converter with all-digital DLLbased calibration, Microelectronic Journal, vol. 46, pp. 970–980 (2015).
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• [9] Adapa A. K., John V., Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters, Proceedings of 5th India National Power Electronics Conference, Shibpur, Howrah, West Bengal, India, pp. 1–5 (2011).
• [10] GaN Systems Inc., GS66504B-EVBDB GaN E-HEMT Daughter Board and GS665MB-EVB Evaluation Platform, User’s Guide, GS66504B-EVBDB (2016).
• [11] Phothi J., Koseeyaporn J., Wardkein P., Independent Rise and Fall Edge Dead time Generator Based on Monostable Multivibrator Circuit, Proceedings of 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, Phetchaburi, Thailand (2012).
• [12] Chen H. C., A Dead-Time Generator Based on OPA Slew Rate for Consumer Electronic Applications, Proceedings of IEEE International Conference on Consumer Electronics, Taipei, Taiwan, pp. 137–138 (2014).
• [13] Maxim Inc., DS1100 5-Tap Economy Timing Element (Delay Line), Data Sheet, 19-5735, Rev.3/1.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).