The use of hierarchical structures for design of high-speed digital comparators on FPGA/SoC

• Autorzy: Salauyou V.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a design method of high-speed digital comparators on FPGA/SoC by means of hierarchical structures. A synthesis technique of hierarchical structures for comparators is offered. In this technique, the comparator best hierarchical structure is empirically found for a certain FPGA family. The proposed method allows reducing a delay for 256-bits comparators by 1.245 to 2.516 times as compared with a traditional approach, and for 512-bits comparators by 3.399 times. The method also allows reducing an area by 40.2% on occasion.

Słowa kluczowe

EN

comparator; high-speed; hierarchical structures; system on chip; field programmable logic array; FPGA; SoC

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2016
• Tom: Vol. 62, No. 6
• Strony: 196--198
• Opis fizyczny: Bibliogr. 10 poz., rys., tab., wzory

Twórcy

autor

Salauyou V.

Bibliografia

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Uwagi

EN

The present study was supported by the grant SA11/I/2013 from Bialystok University of Technology and funded from the resources for research by the Ministry of Science and Higher Education.