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A method for testing the performance of a dual-core microcontroller with integrated program and data memory

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Języki publikacji
EN
Abstrakty
EN
The paper presents a set of test procedures for performing an extended test of dual-core microcontroller performance. The procedures described enable the performance of the system to be determined with regard to memory organization, mutual influence of cores and ability to verify the impact of code optimization level. The experimental trials were performed using an LPC4357 microcontroller with onboard FLASH and SRAM memory. The results obtained showed a slight performance drop for the various microcontrollers operating simultaneously in typical conditions. However, with frequent references to a shared memory, the performance drop may reach as much as 80%.
Słowa kluczowe
Wydawca
Rocznik
Strony
320--322
Opis fizyczny
Bibliogr. 9 poz., rys., tab., wzory
Twórcy
  • Electronic Department , Military University of Technology Them. Jaroslaw Dabrowski, 2 Gen. Sylvester Kaliski St., 00-908 Warsaw 49, Poland
autor
  • Electronic Department, Military University of Technology them. Jaroslaw Dabrowski, 2 Gen. Sylvester Kaliski St., 00-908 Warsaw 49, Poland
Bibliografia
  • [1] Gebali F.: Algorithms and Parallel Computing. John Wiley & Sons, Hoboken, 2011.
  • [2] Sondej T., Zagoździński L., Pełka R.: Porównanie wydajności sprzętowego i programowego procesora w układzie FPGA Xilinx Virtex-4. Pomiary Automatyka Kontrola, nr 7bis, 2006, pp. 20-22.
  • [3] Gal-On S., Levy M.: Measuring Multicore Performance. Computer, Vol. 41, Issue: 11, 2008, pp. 99-102.
  • [4] Meihua Xu, Huacheng Yao, XuanHuan: Performance test of dual-core processor system based on NIOS II. 2012 IEEE Symposium on Electrical & Electronics Engineering (EEESYM), 2012, pp. 82-85.
  • [5] Dukyoung Yun, Sungchan Kim, Soonhoi Ha: A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, Issue: 1, 2012, pp. 121-131.
  • [6] Pengcheng Nie, Zhenhua Duan: Efficient and scalable scheduling for performance heterogeneous multicore systems. J. Parallel Distrib. Comput., Vol. 72, Issue: 3, 2012, pp. 353-361.
  • [7] Weicker R. P.: An overview of common benchmarks. Computer, Vol. 23, Issue: 12, 1990, pp. 65-75.
  • [8] NXP Semiconductors, LPC43xx ARM Cortex-M4/M0 multi-core microcontroller. User manual, Rev. 1.9, 2015.
  • [9] Gal-On S., Levy M.: Creating Portable, Repeatable, Realistic Benchmarks for Embedded Systems and the Challenges Thereof. ACM SIGPLAN NOTICES, Vol. 47, Issue: 5, 2012, pp. 149-152.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-0311722c-c6fb-40d9-9cae-684ef319ed97
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