Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

• Autorzy: Domański Krzysztof , Głuszko Grzegorz , Sierakowski Andrzej , Tomaszewski Daniel , Szmigiel Dariusz
• Języki publikacji: EN

Abstrakty

EN

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.

Słowa kluczowe

EN

VeSTIC; VeSFET; logic cell; logic integrated circuit; ring oscillator; parasitic element; oscillation frequency; compact modeling

PL

VeSTIC; VeSFET; komórka logiczna; logiczny układ scalony; generator pierścieniowy; częstotliwość oscylacji; kompaktowe modelowanie

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2018
• Tom: Vol. 9, nr 3
• Strony: 123--132
• Opis fizyczny: Bibliogr. 16 poz.

Twórcy

autor

Domański Krzysztof

• Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland

autor

Głuszko Grzegorz

• Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland

autor

Sierakowski Andrzej

• Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland

autor

Tomaszewski Daniel

• Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland

autor

Szmigiel Dariusz

• Division of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), Warsaw, Poland

Bibliografia

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• [2] W. Maly and A. Pfitzner, “Complementary vertical transistors”, Carnegie Mellon Univ., Pittsburgh, PA, CSSI Tech. Rep. 08-02, Jan. 2008
• [3] W. Maly et al., “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, Proc. 18th Int. Conf. MIXDES, 2011, pp. 145–150
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